USB superspeed peripherals Forum Discussions

Hello, everyone,

I am checking the I2S example (cyfxusbi2sdmamode in SDK 1.1.1). I changed nothing in the firmware. Now I found that BCLK(2.82MHz), MCLK(11.28MHz) and LRCK(44.1KHz) are correct. I tried to send data (not 0 ) in the control center and it shows transfer is successful. But the SD pin are always 0. Did anyone have the experience of I2S?

 Hi, 

In Slave firo sync operation, while the SLWR is asserted, data will be written into the FIFO, on every rising edge of the CLK and the FIFO pointer is incremented. 

Here my question is that, is there any option to sample the data from data bus on the falling edge of the CLK.

Thanks,

Subbarao.

Hello, everyone,     

I am checking the Cyfxusbi2sdmamode example. But the data value in the control center is only 0, so I can not check if the transfer is successful or not by monitoring the SD pin (it is always 0). Could anyone point me out that how to change the transfer vaule (not always 00) in the control center?     

Thank you very much,     

Lehua Chen     

Hello, I try to supply the PLCK with 80MHz sine wave. When I click Transfer Data-In in USB control center, at the first several times, the transfers are correct. Then it will show “BULK IN transfer failed with Error Code: 997”. It does not happen when the PCLK frequency is below 50MHz (throughput: 136MB/s).

Has anybody changed the data in cyfxbulksrcsink and verified the data inside Streamer? 

We want to verify that our firmware and hardware are not dropping frames because of signal integrity.  I'm adding a frame number as the first byte of the data sourced by cyfxbulksrcsink.  Even with the Cypress evaluation board, I'm dropping frames.  The frame number pattern is always the same...if I start with frame number 100, the pattern is 0xAA 0x04 0x0C 0x14 0x1C 0x24 0x28.

I understand why the test pattern 0xAA comes out as the first frame number.  But, why is the next frame number off by 4 and then 8 after that?  The first frame number received should be 0.

Hi all,

How can I check the transfer error status in BULK transfer?

Is there any error status register?

and, if 3 times retry fails, What happens?

also Can the firmware know this situation?

Regards,

HC

Hello,

could Cypress provide some informations about the priorities the threads in the FX3-framework run with?

Background of my question is that I'd like to know which (highest) priorities I could use in my user-application without interrupting/delaying any important threads running in the framework.

Thanks!

Robert

HI,

    I tried to download "my_firmware.iic" to my CY68013A board with two bland new 24LC128 EEPROM(A0,A1,A2:1,0,0 and 1,1,0), below is what i did:

1. Open Cypress suit usb 3.4.7->Cyconsole->EZ-USB interface

2.Select download C:\Cypress\USB\Examples\FX2LP\Vend_ax\Vend_ax.hex to CY68013A's on chip RAM

3.Set Req:0xA9, Value:0x0000, index:0x0000, Length:16, Dir:in,   i got:CD CD CD CD CD.........

4.Set Req:0xA9, Value:0x0000, index:0x0000, Length:1, Dir:out, hex byte: 00

5.Set Req:0xA9, Value:0x0000, index:0x0000, Length:1, Dir:in,  i got:CD again(that means now data be wrote in to EEPROM)

6.Select lg EEPROM->"my_firmware.iic"  i got messagebox: EEPROM NOT ENABLED.

7.I used a oscilloscope to IIC BUS during 0xA9 and lg EEPROM,  i found there is not wave on the BUS!!!

Is there anybody can help me? Thanks! 

Hi,

Does CYUSB3014 require any power-up sequence?

Thank you

Berlin Stas