USB superspeed peripherals Forum Discussions
What is the IO standard on the GPIF pins? LVCMOS-1.8?
Does the FX3 have any internal termination, and if so, how does it deal with the bidirectional nature of GPIF?Show Less
where can the software "GPIF II Designer" be downloaded for FX3 ?
The available GPIF designer is dated from 2003 and seems to have no support for FX3 inside ?
Hi, evvery one.
I'd like to know the information of endpoints,such as the size,the access from ARM core and GPIF, how to configure them……. however,I don't find it in the programmers' manual. The datasheet doesn't include this info also.
so,would you please give me some information about the 32 endpoints in FX3? thanks!Show Less
1,what is the "sockets" ,Are sockets the buffers in Sysmem? Because in the concrete application, the external FIFO connects to the GPIF, the data from the FIFO is written into the sockets, I should know where it is physically.
2,Can you tell me the detail of the data flow from a FIFO to endpoint? I roughly know they are accomplished through the DMA. Can the FIFO to producer sockets be concurrent with the consumer sockets to endpoint? if not, the largest throughput is less than 3.2GPS, it maybe 1.6GpsShow Less
Is the watermark parameter for CyU3PGpifSocketConfigure (for configuring a partial full flag) only relative to the current buffer, or to all the buffers in the channel as a whole?
That is, if I have the slave fifo DMA channel set up with 2 buffers of 512 bytes, and I specify a watermark at 768 bytes (192 samples for 32-bit mode), will the watermark be hit if one buffer is filled but not consumed, and the second is half-full? Or does it only consider the current buffer, and such a watermark will never be hit?
I want to use an oscillator which is easier to find than ITTI's on my FX3 board.
ITTI has no information about the 14400076-19.200MHz crystal on thier website.
Do you have the datasheet of this crystal?
What is the input capacitance of the FX3?
What should be the load capacitance of the crystal?
Ersin OEZALPShow Less
I cannot get the 32 bit sync slave FIFO working. In 16 bit mode the firmware works well and transfers 120MB/s to the host with 16 packets per burst. But the 32 bit mode don´t work, no data is transferred and the CyFxSlFifoPtoUDmaCallback() is never called HW-breakpoint using J-Link debugger). I use a simplest hardware connection: A 100Mhz oscillator on PCLK. WR, CS, A0 and A1 pulled to low; OE, RD, and PKTEND pulled to high. But only the 16 bit mode works.
How can I get this working? I use the beta 3 SDK. In the slave fifo appnote a cannot find a difference between 32 bit and 16 bit mode regarding the control lines.
I used the DVK to see if gpio and the oscillator clocks are synch or not. Based on my test, they are not, Is there any explanation on this? What about if I use CLKIN instead of crystal oscillator?
I am trying to read data on the slave fifo interface. As can be seen on the first page of the attached pdf, the first read attempt succeeds and is stopped after flag A (empty/full fixed to thread 0) indicates fifo empty.
On the second page an example is shown, where data is read using two read accesses. The first access works good, while during the second access the data lines get stuck at 0x0000.At the same time flag A gets stuck high until I reset the FX3 chip. The clock frequency is only 10 MHz.