USB superspeed peripherals Forum Discussions

 hi everyone

I meet aproblem .I have a usb 3.0 board, when it connect with usb2.0 port ,the PC device mananer Recognition as usb2.0 device,when connect with usb3.0 port the PC mananger Recognition as usb 3.0 device .but  the device will be detach secends soon and attach after  secends .USB2.0 is stable。what can be lead this problem .who can help me. 

test SDK 1.2 /1.1/1.1.2

test OS :win 7 64bit /win7 32 bit

It maybe hardware problem.(board is make by myself) Any notices with board

thanks

 Hello

I have been working on FX3 Bulk transfer mode for about an year.

I heard that Isochronous transfer mode is more secure than bulk transfer mode at the aspect of transfer ratio.

Thus, I would like to run my system with Isochronous mode.

For the first step, I have tried with "ISO Loop Auto Example" with "Bulk Loop Test C# Sample example".

But it does not work.

Someone says that "Streamer" is matched to Iso transfer mode, but it is not easy to use.

Please help with the attached projects. 

Thank you very much.

 Hi,

does anybody know why the OS win 8 64bit is telling device supports higher speed at a SS PORT. Althoug the device is connected to FX3 through USB3 SS port and device is signalling SS speed with the SDK function CyU3PUsbGetSpeed?

The FX3 uses in this case I2C bootloader with fallback. First the bootloader of I2C is executed and then this bootloader connects through superspeed and on the SS way the final application firmware file will be uploaded through vendor request and then re connects to super speed. 

Thanks

lumpi

Hi,
I am working on FX3 firmware, my firmware size about 200KB is bigger than the default 180KB in fx3.ld, I changed the fx3.ld file as attached:

SYS_MEM : ORIGIN = 0x40003000 LENGTH = 0x3D000
DATA : ORIGIN = 0x40040000 LENGTH = 0x8000

Also I changed the RTOS heap area in cyfxtx.c

#define CY_U3P_MEM_HEAP_BASE ((uint8_t *)0x40040000/*0x40038000*/)
#define CY_U3P_MEM_HEAP_SIZE (0x8000)

Compiler PASS, but PC host can't build the connection with FX3. If I reduced the file size and used the defualt fx3.ld, everything works normally.

What is my problem and how to fix it? Thank you!

 

Hi,

When I run the USBBulkSourceSink example and try to get the FX3 to switch back to the 2 stage booter by calling the function CyU3PUsbJumpBackToBooter the function returns with  CY_U3P_ERROR_OPERN_DISABLED and according to the FX3APIguide this means that the FX3 2 stage booter doesn't support switching back. Before calling this function the CyU3PUsbSetBootSwitch(CyTrue) is called.

Could anyone help me to get this to work.

Thanks

Sodafarl

 The data sheet specifies a tCTLO (clock to out valid) time of 8ns and a tCOH (clock to out hold) of 0ns.  If this is true then there aren't many devcies that will interface with the CYUSB3014 including another CYUSB3014 or a high speed synchronus FIFO which both require 0.5ns of hold time on a control input.  In my case the CYUSB3014 will be the GPIF master and driving the clock and controls.

I'm looking for clarification of this timing spec.

Thanks, Bill

Hello,

  I have the GPIF controller configured in 32bit synchronous master mode hooked up to an FPGA. I have exported several DMA flags one of them being Thread_0_DMA_Ready, which I use with an IN endpoint. The output DMA flag going to the FPGA is mostly at 0 even if I send multiple IN packets to the FX3. Experimenting with the setup, I found that even when the DMA flag is 0, I can successfully capture and transfer data to the PC (via IN_DATA). My state machine knows to stop capturing data based on the internal GPIF DMA_RDY_TH0 conditional flag, and does not use LD_DATA_COUNT or CMP_DATA_COUNT. As soon as GPIF state machine sees that the internal DMA_RDY_TH0 is 0, it switches to an idle state and this is the only time I see the output DMA flag Thread_0_DMA_Ready going to 1. The output DMA flag stays high for roughly 80 cycles (at 100MHz) then goes down low. Is this behavior expected? 

   Basically, I would like to know what does Thread_0_DMA_Ready indicate when used with an IN endpoint? It seems to me as if though Thread_0_DMA_Ready does not simply mimic the value of the internal conditional falg DMA_RDY_TH0. 

   Should I look I be thinking of Thread_0_DMA_Ready from the FX3 USB's perspective? As in, the IN endpoint thread is "ready" when it has data available to send to the USB controller?

Thank you

Hi,

Can we install two different versions of FX3 SDKs on same developement PC?

Thanks,

Subbarao.

 Hi,

We plan to use the FX3 GPIF II to drive a Xilinx Kintex-7 SelectMap programming interface.

In order to control it properly, we'd like to write/read PROG_B, INIT_B and DONE to/from GPIOs controlled by firmware and use GPIF II just for clock, data and CSI_B.

In fact, we just have to init sequence by firmware with PROG_B/INIT_B then wait for a data in a socket, then send it on the GPIF II data bus and assert CSI_B in the same time data is valid, until there is no more data and DONE pin is driven high.

As the GPIF state machine will rely only on data present in the socket, it should be very simple like that:

IDLE -> Set data on bus -> Hold data on bus to respect FPGA setup/hold requirements -> IDLE ->....

But, what should be the transition trigger from IDLE to Set data on bus? Since it does only depends on data present in the socket? Is DMA_RDY_CT ok? Because it tells DMA is ready, not if a data is present in the socket...

Thanks in advance for the help.

Johan