Does anyone know if it is OK to leave the USB 3.0 1.2V supply pins (and associated logic powered by those pins) unconnected if the FX3 is to be used only for USB 1.1/2.0 communication? I didn't see anything in the datasheet or schematic design checklist (AN70707).

Thanks,
Steve 

Hello! I'm working on a USB-to-GPIF interface and I've noticed a problem. When I have DR_ADDR, DR_DATA, and DR_GPIO actions together in the same state, the data and GPIO lines update immediately as expected but the address lines update one clock-cycle later (with synchronous GPIF). I am using the address counter as the source. Is there a way to fix this to have the address lines drive at the specified time?

Thanks,

Brett

Hi,

Can I improve the download speed via interrupt endpoint (I am using it to configure FPGA), the same way that is explained in

http://www.cypress.com/?app=forum&id=167&rID=59529 or  http://72.3.161.91/?app=forum&rID=63024 ?

I have four endpoints in total. Two bulk (slave FIFO GPIF) and two interrupt, I would like to improve the download speed of the OUT interrupt edn point, but when I configure the cypress with the img file, windows cannot recognize the device anymore.

Thanks,

Nazila

 How can I test the highest speed of FX3 with the development kit & examples in FX3 SDK?

Wich host software and firmware?

Thank you!

Hi,

Can I improve the download speed via interrupt endpoint (I am using it to configure FPGA), the same way that is explained in

http://www.cypress.com/?app=forum&id=167&rID=59529 or  http://72.3.161.91/?app=forum&rID=63024 ?

I have four endpoints in total. Two bulk (slave FIFO GPIF) and two interrupt, I would like to improve the download speed of the OUT interrupt edn point, but when I configure the cypress with the img file, windows cannot recognize the device anymore.

Thanks,

Nazila

Hi,

I am using slave fifo GPIF II. I would like to be able to discard (delete) the content of the GPIF FIFOs from CYUSB3014.  I am using the "CyU3PUsbFlushEp" for both the producer and consumer. But the FIFOs stay unempty! How can I do this?

Thanks,

Nazila

Looking at the supply bypass recommendations there are discrepancies hopefully someone can address. On the AN70707 HW Design Guidelines & Schematic checklist, Section -  Device Supply Decoupling, U3TXVDDQ &  U3XXVDDQ call for 22uF caps. However in the DVK schematics they are 2.2uF. Which is the correct recommendation? Thanks

For the USB connections in the DVK  board schematic, in page 9, the pins from FX3 side: SS_RX_P and SS_RX_N are connected to MICRO_SSRX- and MICRO_SSRX+ on the USB microB side respectively. Is this a typo? Or they have to be swapped for the connection?

Thanks.

Hi,

    we use SlaveFifoSync this example,How to clear the DmaChannel Buffer and Endpoint memory,
I use CyFxSlFifoApplnStop () andCyFxSlFifoApplnStart() to do, Spend a long time.

LIAN,Thanks.