USB superspeed peripherals Forum Discussions
I am currently implementing the FX3 into a project; I have the board and I have the schematics.
My problem is that on page 9 of the schematics there seems to be an error, I didn't catch it until just now:
On the USB3.0 MICRO -TYPE B connector:
- MICRO_SSTX- (connector pin) is connected to SS_TX_M (signal)
- MICRO_SSTX+ (connector pin) is connected to SS_TX_P (signal)
the above part makes 100% sense to me.....
but the following does not make any sense to me whatsoever
- MICRO_SSRX- (connector pin) is connected to SS_RX_P (signal)
- MICRO_SSRX+ (connector pin) is connected to SS_RX_M (signal)
Am I missing something? I admittedly did not catch it initially, my experience tells me that
- MICRO_SSRX- (connector pin) should be connected to SS_RX_M (signal)
- MICRO_SSRX+ (connector pin) should be connected to SS_RX_P (signal)
Is this schematic really representative of the system I have?
Any and all input would be greatly appreciated as I am already to the layout stage and hope to have a functional board the first time around.
Thanks!
-Frank Walker
Show LessDear Sirs,
Our design is to integrate FX3 with data source module. We encounter a DMA no responding problem. Please see the attached PDF file for the detail problem description.
Thank you for your help !
Jeffry Lee
Show Less
Hi,
In my design FX3 firmware is loaded from EEPROM. I want to be sure that after firmware is loaded, it cannot be modified from USB host using A0h vendor request. Maybe I’m too paranoid, but I would like to eliminate a possibility that some bad guy can modify a firmware to destroy expensive hardware. Like a hacker can write a virus to destroy all our hardware around the world.
So the question is how to disable A0h request? Or maybe it is only processed in bootloader code during USB boot and is not available after firmware been loaded? That would be ideal.
Thank you,
Sergey.
Show LessCypress doc says that there's a small break time when a certain thread switches its DMA buffer (not switching socket of the thread, but switching to next DMA buffer of the socket), how long is that time roughly? less than 1us or several micro-seconds or more?
Seems this is a difference from the FX2 chip, for FX2, there's no break time when crossing the USB FIFO buffer (e.g. for 4x 512bytes FIFO)...understood that FX3 needs more complicated design (DMA involved), but is there any idea about this breaking time?
Thanks!
Show LessHello,
I am using FX3 as a Device controller used for USB3.0 communication with PC. I'm interfacing an FPGA xilinx Spartan6 to the FX3 with the slave fifo 32 bit by GPIG II following the the guide of the website. For testing communication I'm using the loopback example of AN65974 downloaded folder and I custmoized the GPIF for my board with the GPIF tool . With the USB Control Center I stream data to the FPGA and it write back to the fifo correctly (I can watch them with chiscpope analyzer). Something fails in the communication from fx3 to pc. In the the attached file you can see the error in the 4th byte of 3rd line, 5th line, 7th line and so on.
Each line of the GPIO are right routered to the FPGA and equalized, I don't think there are problem with signal integrity. The hardware it seems ok.
Could you help me please?
thanks a lot
Show LessHello,
Who can send me a source code of Demo Firmware(cyfxuvc.img) in the website http://www.cypress.com/?rID=72599.
Thanks.
Allen