USB superspeed peripherals Forum Discussions
Hi support,
I'm thinking of configuring HX3 with an external I2C EEPROM. If I only save configuration data to EEPROM and there is no need to change the data, is there any possibility to write to EEPROM from HX3?
If there is no particular writing to be done, I am thinking of setting the Write Protect pin to H to prevent writing.
Best regards,
KOki
Show LessIs there CYUSB3014 cyusb3 driver for "Windows 11/Qualcomm ARM" platform?
Regards,
Kyle
Dear experts:
please give us help。
we are interfacing CYUSB3065-BZXI to onsemi AR0521,something happened and we can not find the root cause.
[Problems]
UVC App only shows green images。we can see luminance changes when we cover and open the lens of sensor.
[Configurations]
USB Peripherals: CYUSB3065-BZXI
Sensor:onsemi AR0521
FX SDK version: EZ-USB FX SDK v1.3.5
AR0521 parameters:Mipi-4lanes, 1920*1080*8bit*30fps, 477Mbps/lane
CX3 mipi receiver configurations:
[Validations]
> Sensor register can be read and write rightly.
> PCLK,HSYNC,VSYNC can output valid signals.
> UART logs
> USB data from wireshark. all streaming data are 0x35.
> CyU3PMipicsiCfg_t mipiConfig_AR0521_RAW8_Resolution1;
> usb descriptor definitions(see attachments)
> It failed after I tried by these:
EZ-USB™ CX3: Interfacing with the onsemi AR0234CS ... - Infineon Developer Community
Streaming RAW10 Format Input Data to 16/24-bit Output Format in CX3 MIPI CSI-2 (infineon.com)
Show Less
Hello,
I'm trying to implement error handling for UVC controls on CX3. When a control is set to an invalid value, the device should respond with a STALL condition. This in turn causes the host driver to query the error code in a separate control transfer.
To do this, I need to read all of the OUT data of the control transfer, validate it, and decide whether to set the STALL condition. However the documentation for CyU3PUsbGetEP0Data has this:
If the control request is to be failed with a STALL handshake, the stall
call has to be made before all of the OUT data has been read. The request
will be completed with a positive ACK as soon as all of the OUT data has
been received by the device.
Is there any way around this limitation? I expected to have some way to keep EP0 in forced NAK until the firmware decides what to do, but nothing I have tried seemed to work.
Thanks!
Show LessI use the resolution 1600*1200 and set it according to 30fps, but the actual frame rate is only 15fps, the main modifications are as follows, please help me to see what the problem is?
1
/* Class specific Uncompressed VS Frame Descriptor 1 - uxga@30fps */
0x1E, /* Descriptor size */
CX3_CS_INTRFC_DESCR, /* Descriptor type */
0x05, /* Subtype: Uncompressed frame interface */ 0x01, /* Frame Descriptor Index: 1 */ 0x00, /* No Still image capture supported */ 0x40, 0x06 Subtype: Uncompressed frame interface*/
0x01, /* Frame Descriptor Index: 1 */
0x00, /* No Still image capture supported */
0x40, 0x06, /* Width in pixel. 1600 *///0X640
0xB0, 0x04,
/* Heigh t in pixel: 1200 *///0 X4B0
0x00, 0x80, 0xEE, 0x36, /* Min bit rate (
bi ts/s): 1600 x 1200 x 2 x 30 x 8 = 921,600,000 *// 0x36EE8000 0x36EE8000 0X36EE8000 0x00, 0x80, 0xEE, 0x36, /* Max bit rate (bits/s): Fixed rate so same as Min */ 0x00, 0x98,
0x3A, 0x00 , /* Maximum video or still frame size in bytes (Deprecated): *///1600*1200*2=3840000//0X3A9800
0x15, 0x16, 0x05, 0x00 , /* Default frame interval (in 100ns units): (1/30)x10^7 */ 0x01, /* Frame interval type : No of discrete intervals */ 0x15, 0x16, 0x05, 0x00 , /* Frame interval 3: Same as Default frame interval */
2 uint8_t const gluxgapProbeCtrl[CX3_APP_MAX_PROBE_SETTING] = {
// uint8_t const gl1080pProbeCtrl[CX3_APP_MAX_PROBE_SETTING] = {
0x00, 0x00, /* bmHint : No fixed parameters */
0x01, /* Use 1st Video format index */
0x01, /* Use 1st Video frame index */
0x15, 0x16, 0x05, 0x00, /* Desired frame interval in 100ns = (1/30)x10^7 */
0x00, 0x00, /* Key frame rate in key frame/video frame units */
0x00, 0x00, /* PFrame rate in PFrame / key frame units */
0x00, 0x00, /* Compression quality control */
0x00, 0x00, /* Window size for average bit rate */
0x00, 0x00, /* Internal video streaming i/f latency in ms */
0x00, 0x98, 0x3A, 0x00, /* Max video frame size in bytes = 1600 x 1200 x 2 */
#ifdef CX3_UVC_1_0_SUPPORT
0x00, 0x90, 0x00, 0x00 /* No. of bytes device can rx in single payload: 36KB */
#else
/* UVC 1.1 Probe Control has additional fields from UVC 1.0 */
0x00, 0x90, 0x00, 0x00, /* No. of bytes device can rx in single payload: 36KB */
0x00, 0x60, 0xE3, 0x16, /* Device Clock */
0x00, /* Framing Information - Ignored for uncompressed format*/
0x00, /* Preferred payload format version */
0x00, /* Minimum payload format version */
0x00 /* Maximum payload format version */
#endif
};
3CyU3PMipicsiCfg_t OV5640_YUY2_UXGA =
{
CY_U3P_CSI_DF_YUV422_8_2, /* CyU3PMipicsiDataFormat_t dataFormat */
2, /* uint8_t numDataLanes */
2, /* uint8_t pllPrd */
89, /* uint16_t pllFbd */
CY_U3P_CSI_PLL_FRS_250_500M, /* CyU3PMipicsiPllClkFrs_t pllFrs */
CY_U3P_CSI_PLL_CLK_DIV_4, /* CyU3PMipicsiPllClkDiv_t csiRxClkDiv */
CY_U3P_CSI_PLL_CLK_DIV_4, /* CyU3PMipicsiPllClkDiv_t parClkDiv */
0, /* uint16_t mClkCtl */
CY_U3P_CSI_PLL_CLK_DIV_2, /* CyU3PMipicsiPllClkDiv_t mClkRefDiv */
1600, /* uint16_t hResolution */
50 /* uint16_t fifoDelay */
};
4 OV5640 register settings
0x3035,0x11,
0x3036,0x54,
0x3037,0x13,
smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/%E8%B6%85%E9%AB%98%E9%80%9FUSB%E5%A4%96%E8%AE%BE/CX3-OV5640-%E5%B8%A7%E7%8E%87%E9%97%AE%E9%A2%98/td-p/706749
Show LessHello, when I use the stream_out routine of AN65974 to read data, I can see through the logic analyzer that the read data has the interference item 00000000. Why does this phenomenon occur?
good luck!
cool breeze
smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/%E8%B6%85%E9%AB%98%E9%80%9FUSB%E5%A4%96%E8%A8%AD/CYUSB3014-use-SlaveExample/td-p/707738
Show LessHi,
New to FX3. How FPGA , GPIF, AUTO DMA Channel and AUTO BULK IN work together?. what is role of ZLP?.
Hello, I have the following needs now, but I don’t know where to start. I hope to get some advice.
Requirement: I want to use the cyusb3014 chip to build a bidirectional transmission channel. The transmission from the PC side to the FPGA side is the primary path. The amount of data to be transmitted is large. The transmission from the FPGA side to the PC side is the secondary path. The amount of data to be transmitted is small. I hope that the primary and secondary paths are Can transmit at the same time without interfering with each other. Hope you can give me some advice.
wish you a happy life!
cool breeze
smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/%E8%B6%85%E9%AB%98%E9%80%9FUSB%E5%A4%96%E8%A8%AD/cysub3014/td-p/710378
Show LessHi Dears:
We are developing CYUSB3065+AR0521, host app can not streaming images. please give us support, thanks.
(1) Sensor configurations:
RAW8,mipi 4lanes, 2600x1952,8bit 60fps
(2 ) mipi receiver configurations
(3) UART logs
Prod = 104 Cons = 104 Prtl_Sz = 11264 Frm_Sz = 2540944 B
Prod = 104 Cons = 104 Prtl_Sz = 19744 Frm_Sz = 2549424 B
Prod = 104 Cons = 103 Prtl_Sz = 10528 Frm_Sz = 2540208 B
Prod = 104 Cons = 104 Prtl_Sz = 10528 Frm_Sz = 2540208 B
Prod = 104 Cons = 104 Prtl_Sz = 10800 Frm_Sz = 2540480 B
Prod = 104 Cons = 104 Prtl_Sz = 11296 Frm_Sz = 2540976 B
Prod = 104 Cons = 104 Prtl_Sz = 11020 Frm_Sz = 2540700 B
Prod = 104 Cons = 104 Prtl_Sz = 10528 Frm_Sz = 2540208 B
Prod = 104 Cons = 105 Prtl_Sz = 14128 Frm_Sz = 2543808 B
Prod = 104 Cons = 103 Prtl_Sz = 10532 Frm_Sz = 2540212 B
Prod = 104 Cons = 104 Prtl_Sz = 10532 Frm_Sz = 2540212 B
Prod = 104 Cons = 105 Prtl_Sz = 14892 Frm_Sz = 2544572 B
Prod = 104 Cons = 103 Prtl_Sz = 10532 Frm_Sz = 2540212 B
Prod = 104 Cons = 104 Prtl_Sz = 12332 Frm_Sz = 2542012 B
Prod = 104 Cons = 105 Prtl_Sz = 14920 Frm_Sz = 2544600 B
Prod = 104 Cons = 103 Prtl_Sz = 10532 Frm_Sz = 2540212 B
Prod = 104 Cons = 104 Prtl_Sz = 10532 Frm_Sz = 2540212 B
Prod = 104 Cons = 104 Prtl_Sz = 10976 Frm_Sz = 2540656 B
Prod = 104 Cons = 105 Prtl_Sz = 14584 Frm_Sz = 2544264 B
Prod = 104 Cons = 104 Prtl_Sz = 14016 Frm_Sz = 2543696 B
Prod = 104 Cons = 103 Prtl_Sz = 13876 Frm_Sz = 2543556 B
Prod = 103 Cons = 104 Prtl_Sz = 14880 Frm_Sz = 2520000 B
Prod = 104 Cons = 104 Prtl_Sz = 11016 Frm_Sz = 2540696 B
Prod = 104 Cons = 104 Prtl_Sz = 14588 Frm_Sz = 2544268 B
Prod = 103 Cons = 103 Prtl_Sz = 19084 Frm_Sz = 2524204 B
Prod = 104 Cons = 104 Prtl_Sz = 14936 Frm_Sz = 2544616 B
Prod = 104 Cons = 104 Prtl_Sz = 14928 Frm_Sz = 2544608 B
Prod = 104 Cons = 103 Prtl_Sz = 10600 Frm_Sz = 2540280 B
Prod = 104 Cons = 105 Prtl_Sz = 14880 Frm_Sz = 2544560 B
Prod = 103 Cons = 102 Prtl_Sz = 1120 Frm_Sz = 2506240 B
Prod = 104 Cons = 104 Prtl_Sz = 14428 Frm_Sz = 2544108 B
(4) PCLK, HSYNC, VSYNC signal, hsync signal looked wrong something.
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Hi,
I'am using SDIO port 0 on FX3S chip to communicate with a demod device. I Have configured bus width to 1bit initially, using below code snippet.