Just cranking on the default example included with the EZ-USB FX3 SDK for the slfifosync example.  There is a flag in the cyfxslfifosync.h file, CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT, which looks like it ought to work.  When I generate config files from the GPIF II Designer, the output files look like they match what would be selected based on that flag value.

I get it to work in 16 bit mode, the default for the example, but switching that flag to 1, setting it up for 32 bit mode, I don't get any data on the host side.  Advice?

-CL

 Hi

when transferring data from FPGA to PC using Cypress Streamer and changing those 2 parameters i see different speeds. It happens that keeping Packets per Xfer at a fixed value and changing Xfers to queue from 64 to 32 i see a grater speed i would expect that queueing more packets reduces CPU overhead and this results in a greater speed...Why this is not happening ?

can anybody give me an explanation ?

regards

Pietro

Hello

I'm currently facing an issue with my access to the eMMC memory. To have a byte write API in upper levels, I implement an eMMC block read-modify-write in the FX3 firmware. Initially, things looked good, however, when I'm testing very high byte addresses (i.e. the ones in the highest few blocks of the big user partition), I find out that it does not work correctly.

Stepping through the whole code with the debugger, everything always worked properly (not a very nice effect, when you try to track down an error). With this result, I started to insert sleeps into the code to make out which wait actually has influence on the issue, and found out that its the one right before writing back the block(s). It's the [CyU3PThreadSleep(1)] statement in the appended code extract.

Any hint, what kind of effect this is? Actually, I'm using debug build configuration, so no "optimizing away" things should happen. Is there any restrictions in accessing the same eMMC block (read-modify-write). I assumed that waiting for read buffer, waiting for completion (DMA methods) should be enough. Is there some additional SIB/eMMC busy flag I'm not aware of?

Hello

I'm referring to the statement

"GPIO[32:30] (PMODE[2:0]) signals should be configured appropriately at FX3 boot-up. After boot-up, these signals can be used as GPIOs." i

which can be found in the "GPIF II Interface" section in AN70707

Trying to use these GPIO, I either end up in CY_U3P_ERROR_BAD_ARGUMENT when trying to enable them as simple GPIO during CyU3PDeviceConfigureIOMatrix or in CY_U3P_ERROR_NOT_CONFIGURED when trying to override them later. I found some "dirty tricks" with writing own API functions to solve that issue, but I think there must be an "official" way through the API to use those pins as GPIO, after all it is mentioned in AN70707. How is it done?

Regards

 Hi,

Is that possible to configure the Cypress FX3 device to allow the USB3.0 and USB2.0 work at the same time? So in Windows, with supported driver, we can see 2 devices attached, where 1 USB3.0 and 1 USB 2.0/1.0 devices.

I seen it possible on some of USB3.0/2.0 PHY chip. Is this possible for FX3? Or there is limitation on FX3 firmware framework that not allow this ? 

I need the Shematic or Pinout for the Aptina Interconnect Board Rev2 to connect my Aptina MT9M114 Modul.

Any Help here ??

Best Regards

Ralf

Cypress Introduces $49 SuperSpeed Explorer Kit to Accelerate USB 3.0 Designs

Kit Leverages Cypress's Programmable EZ-USB(R) FX3(TM) Solution; Demonstrations and Kit Giveaways Upcoming at IDF 2014

SAN JOSE, CA -- (Marketwired) -- 09/08/14 -- Intel Developer Forum (IDF) -- Cypress Semiconductor Corp. (NASDAQ: CY) today introduced a low-cost, easy-to-use development platform that enables designers to add high-performance USB 3.0 throughput to virtually any system. The new SuperSpeed Explorer Kit, now available for $49 online, is based on Cypress's programmable EZ-USB® FX3™ USB 3.0 peripheral controller, which offers the flexibility to address a broad range of applications. Cypress will demonstrate the kit in booth number 780 at the Intel Developer Forum (IDF) in San Francisco from September 9-11, and 100 attendees will receive free kits.

EZ-USB FX3 is the industry's only programmable USB 3.0 peripheral controller. It is equipped with a highly configurable General Programmable Interface (GPIF™ II), which can be programmed in 8-, 16-, and 32-bit configurations. GPIF II allows FX3 to communicate directly with application processors, FPGAs, storage media, and image sensors and provides a data transfer rate of up to 400 Megabytes per second, while using lower power than alternative solutions. The SuperSpeed Explorer Kit easily interfaces with external devices via three accessory boards that connect to Aptina image sensors, Altera FPGAs and Xilinx FPGAs, respectively. The kit also includes an integrated debugger with a standard USB interface to further simplify designs and speed time to market.

Cypress will also be giving away advance copies of the book "SuperSpeed Device Design by Example" by USB expert John Hyde at IDF. The book provides a practical approach to designing and implementing SuperSpeed USB peripherals and includes a series of examples using the SuperSpeed Explorer Kit. Hyde will be signing copies of the book in the Cypress booth and will present on SuperSpeed design on September 10 at 12:30 p.m. at the IDF Networking Plaza Theater.

"With the unique programmability of Cypress's FX3 solution, our new $49 SuperSpeed Explorer kit makes it easier and more cost-efficient than ever before for designers to add USB 3.0 to their next-generation products," said Mark Fu, senior marketing director of the USB 3.0 Business Unit at Cypress. "We look forward to showcasing the kit at IDF, along with our leading USB 3.0 portfolio."

"I have been working with many of Cypress's FX3 customers and wrote my book to address their most common concern of 'getting started,'" said Hyde, who's also a principal at USB Design By Example. "The book covers the end-to-end development process including Windows examples, FX3 firmware examples, GPIF II examples, and even Verilog examples for a CPLD plug-on board that enables you to try a variety of high-performance interfaces to your own hardware. I wanted to make SuperSpeed USB technology more accessible and believe that the book, along with the new Cypress kit, is a good first step in that direction."

In addition to FX3, Cypress will feature other solutions from its USB 3.0 portfolio at IDF, including:

    
• The USB-IF Certified, 4-port EZ-USB HX3 USB 3.0 hub controller, which offers robust interoperability, support for Battery Charging v1.2 and Apple charging standards, and full configurability. HX3 targets docking stations, monitors, Ultrabook™ devices, digital TVs, set-top boxes, printers and servers.
    
• The EZ-USB CX3™ camera controller, which enables developers to add USB 3.0 to image sensors supporting the Mobile Industry Processor Interface (MIPI) Camera Serial Interface Type 2 (CSI-2) standard. CX3 provides four CSI-2 data lanes with speed up to 1 Gbps per lane, and it supports uncompressed video streams.
    
• The EZ-USB FX3S™ RAID-on-Chip controller, which integrates storage host controllers that enable developers to add support for SD/eMMC memories and SDIO devices to their system.
   

 Hi,

I am just reading into the FX3 Programmers Manual. It looks like the API is based on ThreadX. If I understand correctly, it is necessary to use ThreadX when I want to use FX3 (as there is  no way to use it without using the API provided by Cypress).

Do we need to license ThreadX then, or is there a respective license agreement between Cypress and ExpressLogic (ThreadX programmer)?

Regards,

Thomas