USB superspeed peripherals Forum Discussions

 I am using the cypress UVC example AN75779 , but when i use the cypress supplied gpif state machine i get backflow detected message and when i check the error is CYU3P_PIB_ERR_THR0_WR_OVERRUN.

I am sure that i have initiated the address and data counters properly. Is there any possible solution to this problem ??

Rags

Hi,

I am checking the Slave FIFO interface on FX3 superspeed explorer kit connected to Xilinx SP601 FPGA Board.

I have successfully done the evaluation on the StreamIN & Loopback modes. I am facing some issues on the ShortPacket & ZLP modes.

As per the application note - AN65974 , i have changed the SW8 on the FPGA board & loaded the binary named as "SF_shrt_ZLP.img" which came with the application note. After that i have Opened the control Center -> selected the Bulk IN Endpoint -> Clicked 'Transfer Data-IN '

I am getting the following error "BULK IN transfer failed with Error Code:997"

Am i missing something ? Any immediate help will be greatly appreciated.

Thank you,
 

Regards,

Shanthakumar

To interfacing with external device, I'm trying to test using CYUSB3014.

I configured GPIF to slavefifo, and I checked operation correctly in case of 8 bit data width mode.

I tried to slavefifo 16 bit mode for increasing throughput.

But it is not working correctly.

Output data is Ok only DQ[7:0]. DQ[15:8] is always zero.

I guess, it is not losing even byte data.

Only 8 bit data is output.

For example, If I sent 0x12345678 data, then the following data is output each clock.

0x0078 0x0056 0x0034 0x0012.

The changes to the 16 bit mode are as follows :

GPIF_BUS_CONFIG :

     * BUS_WIDTH : 0 --> 1

     * ADR_CTRL : 0 --> 5

This was a reference to GPIF II designer example. (sync_slave_fifo_2bit.cydsn)

Here's the scenario: the GPIF generates the data and passes it through the manual DMA channel to the USB side. The data generation is non-stop, so if the host is not reading the data, what happens to it, at what stage, and is there a way to signal when it happens (via events/interrupts)? Please, provide the detailed description of data flow from the GPIF unit to USB unit including all the events/interrupts, buffers, buffer wrap ups, buffer commitments and other events that happen during the transfer.

I am using the Cypress FX3 with the latest SDK (1.3.3)

I am polling an I2C slave device for a reply to a command. The slave device will NAK its address until processing is complete and data is ready.

To do this, I call CyU3PI2cReceiveBytes periodically to try to read data. I use its return value as well as the return value of CyU3PI2cGetErrorCode to determine if the read was successful or if the slave NAKed its address.

I am monitoring the I2C bus with a Saleae logic analyzer.

As shown in the image, after the host finishes transmitting the 9th clock pulse, it fails to retake control of the data line to produce a valid stop condition.

The I2C specification requires all transactions to start with a start condition and end with either a restart or a stop condition.

In addition to this, the slave component we use is specifically sensitive to missing stop conditions. It’s unclear if it’s sensitive to missing stop conditions while ACKing its address, but without producing this stop condition, I can’t tell. 

Source snippet:

CyU3PI2cPreamble_t preamble;
CyU3PReturnStatus_t status = CY_U3P_SUCCESS;

preamble.length = 1;
preamble.buffer[0] = (device_address | 0x01); //address here is already left shifted.
preamble.ctrlMask = 0x0000;

CyU3PThreadSleep( 2 );
status = CyU3PI2cReceiveBytes( &preamble, buffer, count, 0 );

In our newly developed board, the FX3 bootloader enumerates as VID/PID = 0x04B4/00BC. We found that our PMODE setting is 111 instead of F11 (This was caused by connecting PMODE[2] to an FPGA input that has an internal pullup that can't be turned off before configuration).

The question is: Is this behavior documented somewhere ? Having a different PID is perfectly fine, but the tables in the programming manual don't list the combination PMODE[2:0] = 111.

On the other hand, I did find the PID=0x00BC mentioned in AN76405 on page 10 (4.3.8). The document says
"The bootloader may boot with VID=0x04B4/PID=0x00BC or VID=0x04B4/PID=0x0053 based on the setting of the PMODE pins", but gives no hint of how to set PMODE[2:0] to use this feature.

Is there another manual that clarifies this beahavour ? Can we leave the board design as it is or do we risk that it won't work with future revisions of the FX3? Which is the PMODE setting to use 0x04B4/0053 ?

Hi 

I have changed the GPIF to accommodate the 12bit sensor parallel input.

Also I want to tweak the uvc to get only Y component because my sensor will capture only the grayscale data.

How do I modify the FX3 AN75779 application to accommodate this.  Any help or pointer to move a head on this is highly appreciated.

Regard

TM

Hi

I want to transfer data from two ADC (ads1298 24-bit, 8-channel ADC chip with SPI interface) to my pc.can I use CYUSB3KIT-003 for SPI connection ? and because I want to sample signal , I need usb 3

Hi all,

I see that cyfwstorprog.exe utility can write a firmware into eMMC/MMC boot area partitions 1 and 2. But once the firmware is written, can the boot partitions be deleted or updated? The "-delpart" command seems to works on user partitions only...

Thanks,

Davide