USB superspeed peripherals Forum Discussions
Hi,
I am trying to test how the DMA_Ready flag works. For that I use a very simple interface and state machine, that would allow me to monitor the flag. See the attached GPIF designer screenshots for the interface and the state machine.
I have setup with a DMA channel from the GPIF to USB, in auto mode. The channel uses 2 buffers, each with size 16 bytes.
The GPIF clock is provided externally, using the positive clock edge.
On the attached waveform snapshot, cursor A indicates the point when WR goes low. After that there are 4 clock cycles that read 4 32 bit words (16 bytes), and on the third positive clock edge the DMA_Ready flag goes low.
Cursor C is when the DMA_Ready goes high again, after the socket has switched to the second buffer. 4 more words are clocked in, and then on the first positive clock edge the DMA_Ready goes low. There is not 3 clock cycles delay this time - only one. Why? Is this normal?
Thank you,
Dimitar
Show LessI am laying out a new pcb for FX3 and was wondering if I could get away with 6 layers only, instead of 8 layers as used in the development kit? The reason for this is strictly cost reduction WITHOUT compromising data transfer speed and signal quality.
We are using the full 32-bit GPIF bus for communication between FX3 and a slave device, and there are hardly any unused pins (5 or less) on the 121-ball 0.8 mm FX3 IC.
Thanks
Mak
Show Lesshi i'm change an75779 example into 32bit data width
the device is emulated and data is transfered about few package then stoped (capture by bus hound) the fx3 program is runing "tx_thread_schedule" & "tx_thread_system_suspend" threads
but 8bit/16bit firmware works fine
then i change my program into uvc + slavefifo from "FX3 firmware for streaming UVC Data from an FPGA" this post
i found the flaga and flagb didnt change when i try to write data into fifo. i checked all ping is fine (rd/oe/pktend are high addr/wr/cs are low)
what the problem should be?
Show LessI have a design that sends 8-bit data from an FPGA to the FX3. I have a manual DMA channel setup that has 4 buffers. When the application starts I can see from UART debug that it fills the 4 buffers but then it stops. The FLAGA goes low and no more data can be sent. Any idea why this is happening? Is it because the host isn't requesting this data so it just waits until it does? I am using the slave fifo code but I am using my own FPGA logic.
Thanks
Jon
Show LessHi,
I am trying to change the buffer size for DMA and number of buffers. I'm talking about CyU3PDmaMultiChannelCreate function. Right now we have about 36k buffer size and 3 as buffer count. We want to decrease size and increase count.
Thanks in advance!
David
Show LessHi,
I am not sure if this is possible but very much desired by us:
Is there any tool to create a GPIF II Designer project from cycx3gpifwaveform.h file?
Thanks in advance!
David
Show LessHi,
I'm implementing a GPIF interface between the FX3 and a Xilinx FPGA. I see there are various bit streams to load into the Spartan 6 eval board to demonstrate various types of USB 3 streams/connections, but I cannot find the FPGA source files for those Spartan bitstreams. Are these available as examples of implementing an FPGA -> FX3 interface ? If so can anyone point me at them ?
Thanks
Tony
Show LessHi,
I am creating an USB composite device. In this, there are two DMA Manual OUT Channels (CPU to USB endpoints). I have two separate functions, each of them use CyU3PDmaChannelCreate to create these DMA Manual OUT channels.
Following are the channels:
1) End point 0x81, Manual OUT ie CPU to Socket ID 1
2) End point 0x82, Manual OUT ie CPU to Socket ID 2
Is it correct to use two separate CyU3PDmaChannelCreate for creating the above channels, both having CPU as the producer. Or shall I use the
CyU3PDmaMultiChannelCreate instead of this?
Show LessHi
I am using SlaveFifoSync sample to learn how Fx3 working. I made an USB loopback firm (EP0x01 for procedure, EP0x81 for consumer) and use Control Center applicaton to send and get data. This is my problem
Ep0x81 can not recieved data when EPpx01 send 1024 byte. It 's OK when i sent 1023 byte or 1025 byte.
Below is my firm configuration infomation
epCfg.burstLen = 16;
dmaCfg.size = size * 16;
dmaCfg.count = 2;
please show me how to get exactly 1024 byte without sent more 1 byte of dummy data?
Show LessHi,
When we configure the end points and the DMA Channels for CX3 board what are the things to be taken care of? I know the endpoint should be as specified as in the descriptors. What about the DMA producer/consumer sockets? Can I use any socket? For example, if a project use socket CY_U3P_UIB_SOCKET_CONS_1, can I change it to CY_U3P_UIB_SOCKET_CONS_10 and run?
Show Less