I have developed an FPGA based Infrared Imaging system. The FPGA drives the sensor and reconstructs a 720p format video from the data captured from the sensor. I can generate the 8 or 10 bit raw data, Syncs(and blanking).
I now want to be able to convert this 720p video into a USB video format. I purchased the FX3 Super speed EZ kit and a HSMC interface board to connect with my FPGA development kit.
I perused the AN75779 application note and have a few questions:
1. The AN75779 application is tailored for the Aptina MT9M114 image sensor. If I can get my timing signals(syncs and pixel clocks) to match those of the Aptina sensor, will I simply be able to use the code in the application note?
2. If not, what modifications are required? The SensorScaling_HD720p_30fps() and SensorScaling_VGA() functions are primarily used for controlling the image sensor(correct me if I'm wrong). All I have is a video stream with 8 bit parallel data, FVAL, LVAL, Pixel Clock and DATAVALID signals. What else will be needed to read video stream from the FPGA?
Thank you for your time and patience. This is my first ever project with FX3. Please do correct me if I'm missing something.Show Less
I would like to know if we can use a hub with a fx3 and how to communicate with each USB device if it is the case, do I need to create software threads?
we will need to but a USB vendor ID in order to release a product.
I have seen that some commercial products use the Cypress vID, even though this is only allowed under special circumstances from USB.org.
As we need very few pIDs, is this an option and where can we find the forms/contracts for it?
Thank you.Show Less
There is only one jtag on my board. And my firmware doesn't work correctly. Could I use a jtag adapter to debug the firmware? And I have a xilinx jtag adapter. Does it work with FX3S?
I doesn't find the manual about how to use a jtag adpater to debug with fx3s. Could someone give me a link about how to use the jtag adpater.
Thanks a lot.Show Less
I'm dealing with USB-IF certification for a device build using a FX3S. The test performed with USB 3 Gen X Command Verifier (Chapter 9 Tests) goes smooth for the USB3.0 part but, if I put an USB2.0 hub in the middle and attempt the USB2.0 part there is a fail:
Now Starting Test: L1Suspend/Resume Test (Configuration Index 0)
Start time: Mon Aug 1 14:54:36 2016
Checking Device Under Test for LPM L1 Compatibility...
USB version of device is 2.10.
DUT IS compatible with LPM.
LPM IS required for DUT
USB 2.0 Extension Descriptor bmAttributes:
LPM Capable = 1
BESL and Alternate HIRD Supported = 1
Baseline BESL Valid = 0
Deep BESL Valid = 0
Baseline BESL: 0d
Deep BESL: 0d
Device Under Test is LPM Compatible.
Upstream port is LPM Compatible.
Parent port of DUT does not support L1C.
Stop time: Mon Aug 1 14:54:37 2016
Duration: 1 second.
Stopping Test [ L1Suspend/Resume Test (Configuration Index 0):
Number of: Fails (1); Aborts (1); Warnings (0) ]
Does somebody know what "L1C" means (above sentence "Parent port of DUT does not support L1C") ?
Is there some FX3 fw example on how to correctly manage USB2.0 LPM L1 compatibility?
Thanks a lot,
I try to create an automatic DMA channel with SPI as the consumer. This is how I go about doing this:
CyU3PMemSet((uint8_t *)&dmaConfig, 0, sizeof(dmaConfig)); dmaConfig.size = pageLen; dmaConfig.count = 0; dmaConfig.prodAvailCount = 0; dmaConfig.dmaMode = CY_U3P_DMA_MODE_BYTE; dmaConfig.prodHeader = 0; dmaConfig.prodFooter = 0; dmaConfig.consHeader = 0; dmaConfig.notification = 0; dmaConfig.cb = NULL; /* Channel to write to SPI flash. */ dmaConfig.prodSckId = CY_U3P_UIB_SOCKET_PROD_1; dmaConfig.consSckId = CY_U3P_LPP_SOCKET_SPI_CONS; status = CyU3PDmaChannelCreate( &glSpiTxHandle, CY_U3P_DMA_TYPE_AUTO, &dmaConfig );
The execution of CyU3PDmaChannelCreate is not succesful.
If CY_U3P_UIB_SOCKET_PROD_1 is replaced with CY_U3P_CPU_SOCKET_PROD and CY_U3P_DMA_TYPE_AUTO is replaced with CY_U3P_DMA_TYPE_MANUAL_OUT then the function succeeds.
Do you understand what I am doing wrong?
This is with reference to the UVC_AN75779 application note(implementing an image sensor using Cypress FX3).
The sensor board eventually pass SYNC and Clock information to the GPIO pins on the FX3 board. Specifically, the application note is written for MT9M114 sensor.
Does anyone know what the timing specs for this interface are?
Specifically, what are the Vertical and Horizontal Syncs and Blanking Periods(in terms of number of clock cycles). Also, what is the clock frequency(PIXCLK) for which this application note is configured for.Show Less
My situation: When I assert 2 signals at zero I remove the VBUS USB power to the FX3 device and I call the CyU3PSysEnterSuspendMode function to put it in low power mode. When I assert either or both the signals at one I assert the VBUS to the FX3, used as wakeup source from suspend state, and I perform a cold reset via the CyU3PDeviceReset function.
Now, the first run is ok (I connect my system to the PC via USB port, used to power the whole board, I assert to zero the 2 signals, the FX3 goes in power down and when I change the state of either or both the signal it exits from suspend and perform correctly the reset), but the second is always wrong (the FX3 goes in power down and doesn't exit from the CyU3PSysEnterSuspendMode function).
What could be the problems?
I've already try to flush and reset the memory associated with endpoints (and re-enumerate the device).
I'm evaluating CYUSB3610 for some test equipments. From Cypress web site, component is in 'sampling' status. It is available in the open market?
I wonder if and how it is possible to connect the FX3 to an USB Type C receptacle and take advantage of the plug reversibility. The basic problem is that on the receptacle the data signals are doubled. So for example the receptacle offers RX1- and RX2- while the FX3 “only” offers RX-. So the question is how I have to interface these lines.
- Only connect one signal (e.g. RX1- to RX-) and leave RX2- open (same for the other signals) as it is done in the CYUSB3610 Evaluation Board http://www.cypress.com/documentation/reference-designs/type-c-gigabit-ethernet-dongle. But I think this way the advantage of the plug reversibility is not applicable, right?
- Shorten both signals (e.g. RX1- shorted with RX2- and connected to RX2) (same for the other signals). I don’t know if the host supports this, I didn’t found any information for this.
- Using a crossbar switch that routes the correct signal to the FX3. (I hope I can avoid this in my design).
Have you other suggestions or did anybody found a good reference design? Thank you for your help.
With best regards