USB superspeed peripherals Forum Discussions
I config FX3 as Slave FIFO 32bit.
If I set FLAGA is Thread_0_DMA_Ready, FLAGB is Thread_0_DMA_Watermark, and set watermark as 4.
Assume DMA buffer is 1024*4.
Because the write is random, I assume the flowing steps:
1. Write 1019 words to fifo;
2. Because no data, wait some cycles;
3. Write 2 words to fifo; (I think FLAGB is not active, because 3 cycles latency)
4. Because no data, wait some cycles, now FLAGB is active;
5. Now data arrived, but we cannot know how many space at DMA buffer? FLAGB=L, FLAGA=H, ( actual has 3 words space);
I think, at step 5, we can only use single write cycle? For example, write one word, and wait 4 cycles, then check the FLAGA?
Show LessDear Sir,
I had found another similar question,CX3 supports resolution?
It seems total payload 3840*2160*30fps*1byte = 248832000 Bytes , which is lower than 300M bytes, CX3 maximum bandwidth.
But, when I use CX3 MIPI Receiver Summary to configure a 4K sensor ,e.g. IMX214, I have to use faster CSI clock (625Mhz)and little blanking.(H-Blanking=40, V-Blanking = 10).
in this configuration, Error free, otherwise, FIFO delay time ERROR will occur.
625Mhz is 1250Mps, is more than 1Gbps per data lane, can CX3 mipi receiver block work at this high speed?
Can you give me some advice which parameters are not configured correctly?
Good time and enjoy FIFA!
Best regards,
David
Enjoy FIFA
Show LessHi,Can CX3 support 4K raw10 @30fps resolution? or 4K raw8 @30fps ?
If CyU3PMipicsiReset() is initialized before CyU3PMipicsiInit (), it will report the error CyU3PMipicsiReset Err = 0x44, and then the initialization succeeds after CyU3PMipicsiInit ().
But now cx3 DMA cannot receive mipi data, and the mipi end can be measured with data,Why can't you receive data?
thank !
Show LessDear all,
I'm using CYUSB3KIT-003 FX3 as a slave FIFO with 32 bit data word and 100 MHz clock sourced from an external FPGA as application processing unit.
I'm new to this so I tried the from cypress provided examples in AN 65974.
I'm aware that cypress provided different firmware images for loopback, short-packet, streamIn and streamOut and the correlated fpga images.
When setting up loopback image in fx3 und FPGA and sending data from the control center into the out endpoint I can see the arrival of data in the fpga via Altera Signal Tap Tool. (See attached image).
FLAG A and B are set High in the beginning and stays high to cause the fpga state machine to get into the loop_back_write state for writing the data back to FX3. This is quite understandable in regard to loopback function.
I want to set up my own control state machine in fpga which can handle stream in and stream out. The fpga example from cypress provide two different fpga images for streaming data in and out. To create one fpga image which can handle both requests I would combine the state machines and would look in the idle state if either flag A and B or flag C and D are set to stream data out and in respectively (and using stremain/out firmware in FX3) However in the beginning Flag A and B are always High (so output buffer in FX3 is not full) and fpga starts to transfer data even when I didn't call XferData with appropiate endpoint. Sometimes I see only flag A is high but not flag B with streamin/out FX3 firmware image.
How is FX3 and/or the fpga statemachine to be configured to only read and write data when user calls api XferData at software on Host-PC?
The reason for this is, that I want to transfer a definite amount of critical data to fpga and send the calculated new data (fixed amount) back via XferData calls. It should not be a continous streaming. Are flags A B C D the correct indication for the fpga to know if it has to send or receive data?
Show LessI have a Denebola kit from e-Con Systems. It was initially configured to send images in a YUY2 format.
I managed to modify the firmware to send image in RGB565 format. For this purpose, I changed the following parameters:
- Camera format registers
- Media Type identifier (GUID)
- MIPI CSI-2 format (in 'CyU3PMipicsiCfg_t')
Since the bits-per-pixel of both formats is the same (16), I can see the video. Even when the camera format is set to YUY2, I can see the image in the PC, but color distorted.
The problem is, I want to stream in RAW8 or RAW10, which have a different bpp. I have changed the same parameters as before, but I can't get it running.
I have read this and this thread, but I'm still missing something. I also posted a case: case#00435749.
Should I change the previous parameters? What values should I use?
Other parameters I think that should be changed, based on what I have read here, are the 'hResolution' in 'CyU3PMipicsiCfg_t', used to calculate BYTE_COUNT; or the MIPI CSI-2 to GPIF bus used in 'CyU3PMipicsiGpifLoad' (now it is set to 16).
Should I change this parameters? What values should I use?
What format, media type identifier and bits-per-pixel should I use in the USB descriptor?
Show LessI have taken the cyusb_linux program (originally written for Qt 4.8), and ported it over to the Macintosh Qt 5.x. I have tested on Sierra for for identifying the USB 3.0 board, and downloading a program to the Superspeed Explorer Kit.
I have not tested *all* functionality. It uses system_profiler on a periodic basis to locate the plugged in device, rather than the udev features.
It is a QT project, and I would recommend compiling it for your machine, as there are some dependencies that may require libraries only installed with Xcode. It uses libusb (like the linux unit), and may require XCode to be installed due to references to libjpeg. Qt Creator can be a pain to set up on the Macintosh, but once it is set up everything goes well.
This was originally written under the GPLV2, so of course, it stays GPL v2.
If anyone is interested in it, you can contact me at wmaxfield at gmail dot com
Show Lesshi all,
I have use 32 bit slave fifo and I want to use GPIO[53:56] as an GPIO used as spi lines for read/write to SPI flash externally connected to a board. And also I need to use Uart for printing debug messages. In FX3, when using 32 bit gpif, then SPI_MOSI and UART_TX are mapped to the same GPIO[55]. Is it possible to use both UART and GPIO in GPIO[55] at a time ?. I tried by reconfiguring the IO matrix, but it wont work. Is there any possible way to do this?
Thanks in advance.
Show LessHi,
Is there an example of how to configure the INT# / CTL15 pin to handle interrupts on the FX3? Using GPIF II Designer I tried configuring an input signal on the INT pin, then defined a state machine that sends INTR_CPU on an INT trigger. I do see the pin go low (Polarity -> Active Low) but never see the firmware callback function called. What else do I need to do?
In the firmware code:
void
AppThread_Entry (
uint32_t input)
{
....
CyU3PGpifLoad(&CyFxGpifConfig);
CyU3PGpifSMStart (START, ALPHA_START);
// register GPIF callback
//CyU3PGpifRegisterCallback(GpifCallback);
CyU3PGpifRegisterSMIntrCallback(GpifSMCallback);
....
}
Show LessHi..
I have implemented a GPIF II interface using an FPGA spartan 6 (XC6SLX9) and a Cypress FX3 (CYUSB3013) controller.
An Isochronous USB endpoint is configured to trasfer the data from the Cypress FX3 to a host PC.
The average data generate rate of the FPGA is about 75Mbps which is generated as distributed chunks rather than as a constant rate data stream. However, I am losing a significant amount of data at the host PC allication.
Followng are some details on my sytsem setup.
PCLK = 60Mhz ; (PCLK is driven by FPGA)
FX3 system clock = 403.2 Mhz; (setSysClk400 = true)
GPIF clock = 100 Mhz ; (pibClock.clkDiv = 4)
USB end point type :- Isochronous
*FX3 Firmware
CY_FX_ISO_BURST = 15;
CY_FX_ISO_PKTS = 1;
epcfg.enable = CyTrue;
epcfg.epType = CY_U3P_USB_EP_ISO;
epcfg.burstLen = CY_FX_ISO_BURST;
epcfg.streams = 0;
epcfg.pcktSize = 1024;
epcfg.isoPkts = 1;
dma_cfg.size = ((1024 + 0x0F) & ~0x0F);
dma_cfg.size *= CY_FX_ISO_BURST;
dma_cfg.count = 8;
dma_cfg.prodSckId = CY_U3P_PIB_SOCKET_0;
dma_cfg.consSckId = CY_U3P_UIB_SOCKET_CONS_2;
dma_cfg.dmaMode = CY_U3P_DMA_MODE_BYTE;
dma_cfg.notification = CY_U3P_DMA_CB_CONS_EVENT;
dma_cfg.cb = 0;
dma_cfg.prodHeader = 0;
dma_cfg.prodFooter = 0;
dma_cfg.consHeader = 0;
dma_cfg.prodAvailCount = 0;
<ENDPOINT>
Type="ISOC"
Direction="IN"
Address="82h"
Attributes="01h"
MaxPktSize="15360"
DescriptorType="5"
DescriptorLength="7"
Interval="4"
<SUPER SPEED ENDPOINT COMPANION>
Type="SUPERSPEED_USB_ENDPOINT_COMPANION"
MaxBurst="14"
Attributes="00h"
BytesPerInterval="3C00h"
</ENDPOINT>
*PC application code to read usb
LONG length = 1024 * 15 * 8 * 64;
std::shared_ptr<uint8_t> image_buffer = std::shared_ptr<uint8_t>(new uint8_t[length]);
QueueSize = int(length / (iso_ep->MaxPktSize * 8));
if ((length % (iso_ep->MaxPktSize * 8)) > 0)
QueueSize++;
for (int j = 0; j < QueueSize; j++){
long len = length / (QueueSize);
std::unique_ptr<uint8_t[]> image_data = std::unique_ptr<uint8_t[]>(new uint8_t[len]);
iso_ep->TimeOut = 5000;
int pkts;
CCyIsoPktInfo * pktInfos;
pktInfos = iso_ep->CreatePktInfos(len, pkts);
if (iso_ep->XferData(image_data.get(), len, pktInfos)){
for (int i = 0; i < pkts; i++){
if (pktInfos.Status == 0 && pktInfos.Length>0)
{
memcpy(&image_buffer[success * iso_ep->MaxPktSize], &image_data[i * iso_ep->MaxPktSize], iso_ep->MaxPktSize);
success = success + 1;
}
}
}
delete[] pktInfos;
}
length = success * iso_ep->MaxPktSize;
Show Less