USB superspeed peripherals Forum Discussions
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Hello,
I'm trying to create an application which starts a SPI DMA transfer of 200 bytes every time there is a positive edge on one of the GPIO pins. Right now, I am polling the pin using CyU3PGpioGetValue and starting the DMA transfer on the positive edge by calling CyU3PSpiSetBlockXfer. However, this does not provide the speed that I need for my application, and the RTOS thread manager interrupting the execution of my application thread occasionally causes the application to miss the edge. I tried configuring a GPIO interrupt handler using the Api provided in cyu3gpio.h, but was unable to get CyU3PSpiSetBlockXfer to run inside of the ISR, as it seems like some API calls cannot be called within an interrupt handler. Is there any way to directly set the DMA controller to read SPI data in on an interrupt, or to allow for running a SPI transfer inside an ISR?
Thank you for any insight.
Show LessI have the CX3 device on a Denebola board and I'm trying to make a Sony IMX219 work.
I got it working in VGA with this configuration:
CyU3PMipicsiCfg_t cfgUvcVga30NoMclk = {
CY_U3P_CSI_DF_RAW10, /* dataFormat */
2, /* numDataLanes */
1, /* pllPrd */
63, /* pllFbd */
CY_U3P_CSI_PLL_FRS_500_1000M, /* pllFrs */
CY_U3P_CSI_PLL_CLK_DIV_8, /* csiRxClkDiv */
CY_U3P_CSI_PLL_CLK_DIV_8, /* parClkDiv */
0x00, /* mclkCtl */
CY_U3P_CSI_PLL_CLK_DIV_8, /* mClkRefDiv */
640, /* hResolution */
0x0A /* fifoDelay */
};
The only "problem" is that it only works when Probe and UVC are configured for 640x482, instead of 640x480, and it sends 2 black lines to host PC, but I can deal with that.
The GPIF bus is 16 bits, and the camera clock has been increased to the maximum value possible that makes it work.
With this configuration, I can easily receive ~110 fps.
Since it works with different camera clocks configurations, but the same MIPI block parameters, I guessed that the MIPI configuration shown above should work for every other resolution. After all, if I don't modify the camera clocks, the bit rate will be the same, and the CX3 MIPI block wouldn't have a problem reading it.
Therefore I changed the camera configuration to work in 720p, with the same clock configuration. And it is not working.
What do I need to change? Why do I need to change something?
I have a byte count to see how many bytes does the DMA send to the USB, and I am getting 0x1CC0E8, when I should be getting 0x1C2000.
Reading in the community, I found that CX3 firmware must be modified to work with MIPI continuous clock. Below are my MIPI signals: yellow is the clock and blue is data lane 0. Is this clock continuous?
I tried doing this when a SET_CUR request arrives from host:
status = CyU3PMipicsiReset(CY_U3P_CSI_HARD_RST);
status = CyU3PMipicsiInit();
status = CyU3PMipicsiSetIntfParams (&cfgUvc720p60NoMclk, CyFalse);
/* Sensor configuration */
As explained in the FAQs. But the result is still the same. Am I doing this wrong? Do I have to do this?
Show LessHi,
I'm working with the FX3 SuperSpeed Explorer kit for linux.
I use the CyUSB Suite for Linux software.
After installing the 'cyusb_linux' application, I checked the device list.
and select to download a firmware image to RAM.
Going back to the Descriptors tab, I could not show the details of the device (List of device, Endpoint OUT/IN...etc,.),
So, I couldn't send data.
The error message is as follows :
I was wondering if there was a problem installing the application for Linux, or what problem I was having.
Show LessHello everyone,
I am a beingger of FX3
I try sample code "GPIFtoUSB" of SDK
The project would catch GPIF one time when power on and transmit by endpoint 0x81
But GPIF always keeps first state
Question is: how to update state of GPIF continually?
Thanks
Show LessHi,
I have setup with fx3 connected to the fpga fabric of a xilinx zynq 7000 series chip. I am trying to get bulk streaming in for sending image data from the fpga to the host computer using the fx3.
I am able to send data by using the dma ready flag but certain number of bytes go missing at each transfer. I am guessing it is due to the flag latency.
So I am trying to use the watermark to stop this from happening. I am following the example given in http://www.cypress.com/?rID=51581 (AN65974 slave fifo sync example).
But I am unable to get it working, there is no data received in the host side, I get the following error in the control center
"BULK IN transfer
BULK IN transfer failed with Error Code:997"
So no data is being transfered. Can anyone help me out with this? I can share more of my code if necessary.
Thanks
Sri
Show Lesswho can tell me , the fx3 how to detected the speed,
Hello.
What kind of adapter (PCI-X to USB3) will you advise for USB3 port?
Not all computers (many old) have USB3 port..
But there are transitional cards from PCI-X to USB3 on sale.
Please, tell me, what is the best board to put, which one has the best compatibility with your chips (FX3 and CX3) ?
Tell me, did you do such research?
Many Thanks!
Show LessHi,
I have configured the Boot Mode to "SPI, USB on failure". If i want to update the firmware, i have to change the configuration on the PMODE pins to "USB" boot. I'm now asking myself if there is a possibility to download the firmware without changing the PMODE pins? I mean for developemnt it's not a problem. But if we deliver the device and the customer should set some jumpers or press a button to make a firmware update, this wouldn't be very nice. Can we do something by software?
Best regards
Walt
Show LessI'm working with a custom camera frontend that does not follow MIPI-DPHY spec exacty on the clock lane.
The clock lane of this camera does not have HS-ZERO in its LP-HS transition.
The clock is continuous clock mode: LP-HS transition only happen once, clock does not switch back to LP between lines or frames.
Questions:
1) Can CX3 recognize this non-standard clock lane? (NXP IMX6Q SoC can recognize it)
2) How do I check the status of clock lane? (How do I know whether the clock is recognized by CX3 or not?)
Currently I can get the camera frontend to transimit MIPI data, but I don't get the DMA callback on the CX3 side. I don't get any MIPI errors from CyU3PMipicsiGetErrors(). I'm suspecting the clock lane is not recognized by CX3. I want to confirm this. Is there a register that reports this?
3) It it possible to always run the clock lane always in HS mode?
For NXP IMX6Q SoC, I must reset the MIPI DPHY when the clock lane is LP, then do LP-HS transition, then the SoC will recognize MIPI clock. If I reset MIPI DPHY with the clock already in HS mode, then it won't see the clock at all.
Is it also the case for CX3?
Show LessHello,
Image sensor is interfaced with fx2lp in slavefifo mode.image sensor configuration is 60 frames per second with 752x480 resolution.
we are modified cypress control center in order to display image.what is the frame rate that fx2lp can handle?
regadrs,
geetha.
Show Less