USB superspeed peripherals Forum Discussions
EZ-USB FX3 Software Development Kit is updated on Mar 29, 2016, but version is not updated.
It is written in FX3 Programmers Manual (Doc. # 001-64707 Rev. *J) revision history that next version number is 1.3.4.
Do you have any plan to update the version to 1.3.4?
Show LessHi,
I am trying to debug a code for EZ-USB FX3 DVK, I am using OpenOCD, I have followed the instructions given in Section 3.2 of "EzUsbSuite_UG.pdf" carefully. But I get the following Errors
Open On-Chip Debugger 0.8.0 (2014-12-03-15:43)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.sourceforge.net/doc/doxygen/bugs.html
Warn : Adapter driver 'cy7c65215' did not declare which transports it allows; assuming legacy JTAG-only
Info : only one transport option; autoselect 'jtag'
adapter_nsrst_delay: 200
jtag_ntrst_delay: 200
adapter speed: 1000 kHz
trst_and_srst srst_pulls_trst srst_gates_jtag trst_push_pull srst_open_drain connect_deassert_srst
RCLK - adaptive
adapter speed: 1000 kHz
Error: CyJtagDevice Not found
in procedure 'init'
I can't figure out what is wrong.
Can anyone help me out with this? I'm running out of ideas.
Show LessDescription: When the FPGA sends data to the PC through the USB chip, after running for a period of time, the PC will no longer receive data, and the FPGA will not send data anymore. At this point, the USB chip FLAGA signal does not go low, so the FPGA cannot send data all the time.
Question: Why is the usb chip FLAGA signal always high? What caused the usb chip to no longer receive data?
FPGA FLAGA signal
Pc log error:
transfer status: LIBUSB_TRANSFER_ERROR
UHD Error:
The receive packet handler caught a value exception.
ValueError: bad vrt header or packet fragment
terminate called after throwing an instance of 'uhd::usb_error'
what(): RuntimeError: USBError -4: usb rx6 submit failed: LIBUSB_ERROR_NO_DEVICE
transfer status: LIBUSB_TRANSFER_NO_DEVICE
--------------------------------------------------------------------------------------------------------
template <typename buffer_type>
UHD_INLINE typename buffer_type::sptr get_new(const double timeout)
{
if (wait_for_completion(timeout))
{
///*qiaoping
if (result.status != LIBUSB_TRANSFER_COMPLETED)
throw uhd::io_error(str(boost::format("usb %s transfer status: %d")
% _name % libusb_error_name(result.status)));
//*/
if (result.status != LIBUSB_TRANSFER_COMPLETED)
std::cout << boost::format("transfer status: %d") % libusb_error_name(result.status) << std::endl;
result.completed = 0;
return make(reinterpret_cast<buffer_type *>(this), _lut->buffer, (_is_recv)? size_t(result.actual_length) : _frame_size);
}
return typename buffer_type::sptr();
}
Show Less
Hello.
Please, tell us a little about DMA for FX3/CX3
How does it work, how to set it up?
What regimes exist?
How does manual mode differ from automatic?
How to forcefully send (read) a buffer?
Show LessHello,
example from EZ-USB FX3 SDK\1.3\firmware\boot_fw\gpiftousb fit close to my application demands - continuously sample GPIF data, and transfer it to PC. But during tests, i am experiencing missing data collected from GPIF interface.
Tests was performed on FX3 Superspeed Explorer kit. Data for GPIF interface are produced by FPGA connected to kit. It's a simple 14 bit counter at 38MHz clock.
DMA in the example is set to AUTO mode (MANUAL_DMA definition disabled).
To minimize errors on my side, for data collecting i use USB control center utility - transfer file-in function. Bytes to transfer is set to 2MB, and result is in the file.
But each 16kB (0x4000) there are missing data.
Like in the next picture:
In this case it's approximately 26 missing FPGA clocks. Sometimes it rise to more than 400 missing FPGA clocks.
Because of USB 3.0 connection i am expecting continuous data flow.
Slowing down GPIF interface by setting clkDiv=8 doesn't help.
Any hint what am i overlook, or how can improve it?
Best regards,
Slavomir
Show LessHello Cypress Community,
I have some problem with EZ USB IDE on Linux,
On fresh install, I'm able to create/import projects and compile it,
But if I restart workstation, IDE loose connection with toolchain and libraries and I'm not able to build project.
Work around that I found is to delete all folders (IDE folder and SDK folder) and install it again. after this IDE is working again until next restart.
May be someone have solution for this because it's annoying to reinstall SDK after each restart.
Regards,
Sergiu
Hi, I'm using CYUSB3KIT-003 and I implemented the syncronous Slave with state machine of the AN65974 example (32bits). The problem is with some bits of the GPIF II have an offset around 1.2V and the FPGA can't detect the zero level. For some reasons it is influenced with the presence of the watermark flag. The bits afected isn't the same with another FX3.
Do you have any idea what is going on?
Show LessHello!
I had several problems debugging FX3:
1.FX3 receiving data Error in CyU3PDmaMultiChannelCommitBuffer: code 71?
2.FX3can transfer 4Kraw16@30fps?
thanks!
Show LessOv5640 library is closed source. How do we control the gain of ov5640?
Hello.
I downloaded the example UVC+CDC (Cx3UvcOV5640_UVC_CDC).
This is a very good example
But there it is made through DMA. I don't control the UART transferring.
And the message from one COM-port is immediately sent to the second one.
I need to send a message through a virtual com-port when I click my button (for example, one byte).
Suggest, how to do it right?
Show Less