USB superspeed peripherals Forum Discussions

After much frustration with a board I am attempting to debug over JTAG, I decided to try debugging the same firmware on a cyusb3kit-001.  I discovered the kit loads firmware properly.  The way I am able to reproduce this problem is with Segger's "J-Link Commander" and typing "connect" then selecting "ARM9". 

On the CYUSB3KIT-001, I get a good result:

J-Link>connect Please specify device / core. <Default>: ARM9 Type '?' for selection dialog Device>? Please specify target interface:   J) JTAG (Default) TIF>j Device position in JTAG chain (IRPre,DRPre) <Default>: -1,-1 => Auto-detect JTAGConf> Specify target interface speed [kHz]. <Default>: 4000 kHz Speed>1000 Device "ARM9" selected. Connecting to target via JTAG TotalIRLen = 4, IRPrint = 0x01 JTAG chain detection found 1 devices: #0 Id: 0x07926069, IRLen: 04, ARM926EJ-S Core CP15.0.0: 0x41069265: ARM, Architecure 5TEJ CP15.0.1: 0x1D112112: ICache: 8kB (4*64*32), DCache: 8kB (4*64*32) Cache type: Separate, Write-back, Format C (WT supported) ARM9 identified. J-Link>

On my board, I get the following failure message:

J-Link>connect Please specify device / core. <Default>: ARM9 Type '?' for selection dialog Device>? Please specify target interface:   J) JTAG (Default) TIF>j Device position in JTAG chain (IRPre,DRPre) <Default>: -1,-1 => Auto-detect JTAGConf> Specify target interface speed [kHz]. <Default>: 4000 kHz Speed>1000 Device "ARM9" selected. Connecting to target via JTAG TotalIRLen = 4, IRPrint = 0x01 JTAG chain detection found 1 devices: #0 Id: 0x07926069, IRLen: 04, ARM926EJ-S Core Using DBGRQ to halt CPU Resetting TRST in order to halt CPU CP15.0.0: 0x00000000: Unknown implementer code, Architecure Unknown architecture J-Link: ARM9, 0 core ****** Error: Unable to halt CPU core J-Link>

The part number on my board is as follows:

CYUSB3014-BZX

One difference between the two baords is the CYUSB3KIT-001 has a 0.1" 2x10 jtag connector, and my board has the 0.05" 2x5 JTAG header.  I am using the Segger adapter board 8.06.02 J-LINK 9-PIN CORTEX-M ADAPTER.

Are there any special settings to the BOOT pins that are required to enable JTAG?  Is there any special processor wiring connections that might cause this behavior?

Best regards,

Kirk Wolff

Wolff Electronic Design

CY-PRO

Is the windows cpp application for fx2lp compatable with FX3? Where can I download windows cpp application for FX3?

In FX3 firmware, CyU3PEpConfig_t has a field named burstLen. It is the Maximum burst length in packets according to the FX3 SDK Firmware API Guide. But I still do not know how it makes difference in application. Does it affect slave FIFO transferring? Is there any explanation about the concept of burst in the datasheet?

Thank you

Hi,

Before load FPGA bit file, USB Control Center can detect FX3.

But immediately after bit file is loaded, USB Control Center becomes empty.

FX3 clock is generated by FPGA, I've probed the clock: clk_10mhz, it's working fine.

What will cause control center can't find anything? How to debug this issue?

Dear Sir,

I want to call use the pins of XRESET & XSHUTDOWN of CX3 mipi blcok as GPIO in 2-stage boot loader , we can use CyU3PMipicsiInit(), but how to do this call in 2-stage bootloader ?

Thanks.

The datasheet says this event is prompted when set configuration. However, I do not know the exact meaninng of setting configuration. Does it mean downloading the firmware into FX3

I'm following this example: http://www.cypress.com/documentation/application-notes/an84868-configuring-fpga-over-usb-using-cypress-ez-usb-fx3

Using a CYUSB3KIT-003 instead of the 001.

In section 4 Operating Instructions it says to connect some pins (of FX3 SuperSpeed Explorer Kit) to:

• Pin 23 of J7
• Pin 31 of J7
• Pin 27 of J7
• Pin 19 of J7
• Pin 37 of J7

However I don't seem to find the pins on my board. I read: http://www.cypress.com/file/139246/download ​ and on the pinnout description is maps the GPIO's (GPIF II Interface) with other pin names according to use but I don't seem to find a bunch of pins under the name J7 that contains the pins listed.

Couldn't find it either on http://www.cypress.com/file/140296/download

I am looking for a block called J7 that has numerous pins but I cannot find it. This seams as a basic question so I'm sorry about it.

I downloaded the SDK from [ezUSB-fx3-SDK](http://www.cypress.com/documentation/software-and-drivers/ez-usb-fx3-software-development-kit)

I start untar all the files and finally I found a instruction I could use in `cyfx3sdk/FX3_SDK_Linux_Support.pdf` I followed the instructions.

I intstalled JAVA 8 instead of 7. The rest was done as said. I didn't do: export CYUSB_ROOT=$HOME/Cypress/cyusb_linux_1.0.5 because it generates problems.

I had the following problem `Gtk-Message: 16:16:03.497: Failed to load module "canberra-gtk-module"` that I solved using `sudo apt-get install libcanberra-gtk-module`.

So far so good. I run `./cyusb_linux` without any messages. The device is found and the blue led is blinking as it is supposed to.

I go to "Data Transfer" and try to read/send packets using the bulk mode:

The first run I get to errors:

LIBUSB_ERROR NO: -1, LIBUSB_ERROR_IO

LIBUSB_ERROR NO: -7, LIBUSB_TIMEOUT

The second run I get something on the "Data Out" box and only error -7 appears.

This are the terminal messages after 2 tries to send the bulk packets.

```

Bytes sent to device = 0

Bytes read from device = 0

Bytes sent to device = 512

Bytes read from device = 0

```

Could somebody help me here? Thank you very much.

PS: I'm using ubuntu 18.04.