USB superspeed peripherals Forum Discussions

We are using a USB TypeC mux with the FX3 (CYUSB3014BZX).  The TypeC mux requires a bias of 0-2VDC on the super-speed signals, specifically the RX pair.  What is the bias or common mode voltage on the SSTX+/- and SSRX+/- signals of the FX3?

Hi All,

I'm working on Fx3 cypress GPIF Interface. I need to send the data from host to external device through a GPIF interface. I am using DMA_Ready_Flag for Data valid signal to External device and Read signal is from External device to cypress.

The timing diagram of Slave FIFO Read is given bellow.

Q1 why data is sampled after 2nd clock cycle of Flag and read signal is assert?.

Please do the needful.

Thank you

With Beast Regards,

Thrimurthi M

Hai all,

I am working on FX3 cypress. I need to pass the data from Host to External Device (Demod) by using slave FIFO concept but only change is Clock. clock is internal clock.

The GPIF designer as shown in bellow figure.

1.In AN65974 application note given Ready flag takes extra 2 cycle for read transfer from slave FIFO, so that I am using Partial flag as a Data valid signal to Demod device.

2. Read signal is input signal from Demod its tell the BUFFER free in Demod.

3. clock= internal.

4. data bus=16.

water mark value setting:  "CyU3PGpifSocketConfigure (0,CY_U3P_PIB_SOCKET_0,0,CyTrue,1);"

GPIF State machine:

Out put wave from:

The above figure shows the output wave from of Read data from Host to Demod. packet size is 64.

* Yellow wave is Partial flag signal.

* Blue colour wave is data bus.

Q1. why Partial Flag is asserted Before data came? in Given AN65974 note 0 cycle of start transfer.

Q2. In Given AN65974 note FULL/EMPTY flag takes 0 clock cycle at start of data transfer and 2 clock cycle for end transfer. But When I use Full/Empty flag it takes 2 extra clock cycle for start data transfer and Why?.

Q3. how to check Read Signal from External device in state machine?.

Q4. AN65974 section 8.3 given 3 formula for water mark calculation I listed below which one is correct.

"When writing from an external master to the synchronous Slave FIFO:

(a) The number of data words that may be written after the clock edge at which the partial flag is sampled low =

watermark x (32/bus width) – 4

2. When reading into an external master from the synchronous Slave FIFO:

(a) The number of data words available for reading (while keeping SLOE# asserted) after the clock edge at which

the partial flag is sampled asserted = watermark x (32/bus width) – 1

(b) There is already two-cycle latency from SLRD# to the data. Hence, the number of cycles for which SLRD#

may be kept asserted after the clock edge at which the partial flag is sampled asserted = watermark x (32/bus

width) –3."

Thank you.

Best Regards,

Thrimurthi M

I want to use GPIF-II to interface to a device with a 4-bit parallel bus and a 5-pin JTAG. The device needs to be configured via JTAG first. Is it possible to add a JTAG state-machine into GPIF-II ? Once configured via JTAG I then want to capture date from the 4-bit parallel bus

       I have an FX3 board and an FPGA board.  The FX3 design is an 1920x1080@60Hz UVC design in YUV2 format. The FPGA sends video data to FX3 through the slavefifo 32bit interface at 100Mhz. The video is actually from an HDMI input to FPGA.

       In the FX3 FW, the DMA buffer size is set to 32KB, 4 buffers. The size of the UVC payload is 32KB. The FX3 SDK version is 1.3.3.

       The Windows can find the UVC device and the video software, like AMCap, VirtualDub, VLC, can open the UVC device and show the video correctly. But after tens of seconds, the video halts.

       Using the Device Monitoring Studio to capture the USB packages between PC and FX3, the final package to FX3 is to request 32KB data from FX3, but there's no data back from FX3. I have no idea why there's no response from the FX3. I can see from the FPGA the slavefifo is full in such situation.

       After I restart the soft, it can show the video again.

       And I also run the slavefifo and streamer example in the SKD, there's no such issue.

       I have no idea what happen to the FX3 and I don't know how to debug such issue?

       Could it be HW issue?  Any ideas for such issue? Thanks.

Hello.

I am using FX3 cy3014 to develop an image data acquisition and transmission device. The configuration mode is salvefifo mode, and the block transfer data length is 1024 bytes.

1) When USB is set to 1024 bytes blocks for transmission, the host computer uses beginDataXfer acquisition. If the data length is not an integer multiple of 1024 bytes, the USB will crash until the reset signal is sent or power-on is restored.

2) When the USB does not store the integer multiple data of 1024 bytes, the beginDataXfer acquisition is initiated (For example, the transmission rate is slow). BeginDataXfer will take precedence over data sending, and USB will also crash until reset or re-energize.

What are the reasons for these two phenomena and are there any solutions?

Thank you very much.

hello everyone, I have designed a PCB board, there are some problems.

1. when I download the official firmware,the board can show usb3.0, and bulkloop and streamer work ok.

2. when download our firmware, it just work 3 seconds, but when download the same firmware to another board, it works ok.

I can't find which I can do to solve this problem.

     thanks!@