USB superspeed peripherals Forum Discussions

How to clear data in an endpoint for FX3 slavefifo example? What is the related code In slavefifo application note firmware? What should be the C++ code running in the host to match the clear operation in the firmware. Thank you.

I am aware of the cyusb libraries provided for linux, however it seems like more effort than it should be to port CyAPI based code to CyUSB. Is it possible to rebuild CyAPI for linux? or is porting from CyAPI to CyUSB easier than I think?

Thanks

Hi,

I'm trying to read/write data (size : 8MB) to FPGA through GPIF2 interface with fx3 as a master. Example code used for this purpose is AN87216.

I've changed according to my needs. Read will start by checking FLAGA status, instead of that i used FW_TRG with INTR_CPU at RD_CTRL state. When i try to read data from Control center utility, only (2048*16) bytes of data is read. If i try to read again, the following error is shown.

BULK IN transfer

BULK IN transfer failed with Error Code:997

Can you help with start reading data without checking the flag status? I need to get complete data without data loss?

Attaching firmware code and .cydsn folder.

Message was edited by: amal john

I develop my FX3 firmare based on AN65974 "Designing with the EZ-USB FX3 Slave FIFO Interface".

The following code in CyFxSlFifoApplnUSBSetupCB is to clear the data in endpoint.

if ((bTarget == CY_U3P_USB_TARGET_ENDPT) && (bRequest == CY_U3P_USB_SC_CLEAR_FEATURE)

                && (wValue == CY_U3P_USBX_FS_EP_HALT))

{

if (glIsApplnActive)

        {

                if (wIndex == CY_FX_COMMAND_PRODUCER)

                {

                    CyU3PDmaChannelReset (&glChHandleSlFifoCommandUtoP);

                    CyU3PUsbFlushEp(CY_FX_COMMAND_PRODUCER);

                    CyU3PUsbResetEp (CY_FX_COMMAND_PRODUCER);

                    CyU3PDmaChannelSetXfer (&glChHandleSlFifoCommandUtoP, CY_FX_SLFIFO_DMA_TX_SIZE);

                }

                else if (wIndex == CY_FX_RESPONSE_CONSUMER)

                {

                    CyU3PDmaChannelReset (&glChHandleSlFifoResponsePtoU);

                    CyU3PUsbFlushEp(CY_FX_RESPONSE_CONSUMER);

                    CyU3PUsbResetEp (CY_FX_RESPONSE_CONSUMER);

                    CyU3PDmaChannelSetXfer (&glChHandleSlFifoResponsePtoU, CY_FX_SLFIFO_DMA_RX_SIZE);

                }

  CyU3PUsbStall (wIndex, CyFalse, CyTrue);

                isHandled = CyTrue;

        }

}

The corresponding C++ code running in the host computer is as follows:

pCtrlEndpt->Target = TGT_ENDPT;

pCtrlEndpt->ReqType = REQ_STD;

pCtrlEndpt->Direction = DIR_TO_DEVICE;

pCtrlEndpt->ReqCode = 0x01;

pCtrlEndpt->Value = 0;

pCtrlEndpt->Index = WORD(address);

long len = 0;

UCHAR buf;

result = pCtrlEndpt->XferData(&buf,len);

I debug the firmware and see the code can run into the desired if and else branch. But the C++ application waits for a few seconds and return false. How to let pCtrlEndpt->XferData(&buf,len) return true. Thank you.

I need to transfer to PC video data with 120 FPS, 10 bit per pixel, 800x480 resolution. I was wondering if the  EZ USB FX3 can do this. As far as I understand, if I need 10 bit per pixel this is effectively 16, so two pixels take all the 32 bits oft the GPIO and there is no room for LV and FV signals. Am I right? IS there an efficient way to configure the device given the above video parameters?

I am using CX3 with OV12895 image sensor. I am able to capture RAW10 video stream of 4096x3072@ 5 FPS using CX3 MIPI receiver configuration as per CX3_conf_4096x3072_5FPS_working.png

Now, I want to capture RAW10 video stream of 4096x3072@ 10 FPS. I have following questions.

1) CX3_TRM mentions that "CX3 is ideally suited for high-definition or high-speed image capturing applications and is capable of streaming uncompressed video up to 1080p at 30 fps or 720p at 60 fps" but it does not mention about 4096x3072 resolution. Is CX3 capable of supporting video stream of 4096x3072@ 10 FPS ?

2) Assuming that there are no limitations on CX3 for 4096x3072@ 10 FPS, I tried to use CX3 MIPI receiver configuration as per CX3_conf_4096x3072_10FPS_not-working.png, but I have no success. Can you please let me know if MIPI receiver configuration in CX3_conf_4096x3072_10FPS_not-working.png is correct ?

To manage PCLK within supported limits of CX3, I used 24bit (instead of 16-bit) Video format output i.e RGB888 (Input format is is still RAW10). I also used CY_U3P_MIPICSI_BUS_24 while calling CyU3PMipicsiGpifLoad(). I assume that GPIF will receive packed data with this settings ( 4 pixel data in 5 bytes). Is this understanding correct?

3) I expect H-ACtive to be 4096 (same as CX3_conf_4096x3072_5FPS_working.png) but it is 1706.66. Is something wrong? How can I make it greater?

4) What is the formula for computing timing H-ACtive, H-Total, V-Active, V-Total in MIPI CSI2 Inputs (Timing) ?

5) What is the formula for computing timing H-ACtive, PHY Time Delay value, H Active, H Blanking in CX3 MIPI Interface configuration ?

Please help.

Thanks,

TJ

Message was edited by: Tejendra Joshi

We are using a USB TypeC mux with the FX3 (CYUSB3014BZX).  The TypeC mux requires a bias of 0-2VDC on the super-speed signals, specifically the RX pair.  What is the bias or common mode voltage on the SSTX+/- and SSRX+/- signals of the FX3?

Hi All,

I'm working on Fx3 cypress GPIF Interface. I need to send the data from host to external device through a GPIF interface. I am using DMA_Ready_Flag for Data valid signal to External device and Read signal is from External device to cypress.

The timing diagram of Slave FIFO Read is given bellow.

Q1 why data is sampled after 2nd clock cycle of Flag and read signal is assert?.

Please do the needful.

Thank you

With Beast Regards,

Thrimurthi M