USB superspeed peripherals Forum Discussions
Hi,
I'm just got the FX3 SUPERSPEED EXPLORER KIT. Now to test the board I followed the instruction on the "Getting_Started_with_EZ-USB_FX3". However when i try to build any of the exisiting Firmaware Project i get the Error: "
Description Resource Path Location Type
cs-make: *** [cyfx_gcc_startup.o] Error 1 USBBulkLoopAuto C/C++ Problem
"
The console logs are
"
14:26:22 **** Incremental Build of configuration Debug for project USBBulkLoopAuto ****
cs-make all
'Building file: ../cyfx_gcc_startup.S'
'Invoking: Cross ARM GNU Assembler'
arm-none-eabi-gcc -mcpu=arm926ej-s -marm -mthumb-interwork -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wall -g3 -x assembler-with-cpp -I"C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\/fw_lib/1_3_4/inc" -MMD -MP -MF"cyfx_gcc_startup.d" -MT"cyfx_gcc_startup.o" -c -o "cyfx_gcc_startup.o" "../cyfx_gcc_startup.S"
The current directory is invalid.
cs-make: *** [cyfx_gcc_startup.o] Error 1
14:26:25 Build Finished (took 2s.775ms)
"
I installed both EZ-USB FX3 SDK 1.3.3 and Superspeed Explorer Kit Rev (both with the complete setting chosen) but it doesn't work.
Could you please help to solve my problem ?
EDIT:
I found the Problem.
For everyone who has the same Problem. When you import the Project you have to select in the menu to copy the Project into workspace.
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I have an FX3 UVC camera that works in USB 3, but not in USB 2. What I see is a long set of "clear feature" requests, which of course causes the stream to abort. As soon as I get the application started, I get a "clear feature" and the application stops.
I have some questions. The endPointConfig and the dmaMultiConfig setups in the sample are set only for USB 3 information. It seems to me that the packet size and the DMA buffer size/count values need to be tailored to the interface speed, but I don't see that in any of the samples. How is that supposed to work? The bulk packet size is set to 1024, but for high-speed the bulk packet has to be 512. Is the API taking care of that for me?
Does it matter whether the endPointConfig and dmaMultiConfig configuration is done at app init or at app start time? I've seen it done both ways.
Show LessHi,
My application requires two single lane MIPI image sensors (400x400 x 120fps OVM6211).
Is it possible to connect both of these to an FX3 chip, and send back to the PC a single 800x400 x 120fps image?
What's the quickest way to get a prototype of this working? Should I just get a CYUSB3KIT-003, and make a custom PCB to connect the cameras to it?
Many thanks
Hugo
Show LessHi,
In CX3 UVC firmware, if I enable prints in Callbacks (i.e. Setupcb, uvcappdmacallback) firmware hangs in long run. Is there any way to overcome this?
Thanks in advance,
Vignesh Kumar R.
Show LessIn order to follow AN84868 instructions and use FPGA Configuration Utility to program the FPGA it is necessary first to power on the FX3 before powering on the FPGA.
Using my own code, I have seen that the PID changes if the FPGA was powered on before the FX3 device. So I tried to configure it nevertheless with that PID and with my own program. I do succeed on programming the FPGA but then I cannot send the bulk transfers. I think the FX3 never turns into slave fifo mode.
I do send it the B1 command, as I said, if I use my code with the FX3 device it works great when powering first the FX3.
The strangest thing is also that I printed UART messages in the following code snipet from cyfxslfifosync::CyFxSlFifoApplnUSBSetupCB():
Header 1 |
---|
if (bRequest == VND_CMD_SLAVESER_CFGSTAT) { CyU3PDebugPrint (4, "\r\tVND_CMD_SLAVESER_CFGSTAT\r\n", bRequest); if ((bReqType & 0x80) == 0x80) { glEp0Buffer [0]= glConfigDone; CyU3PUsbSendEP0Data (wLength, glEp0Buffer); /* Switch to slaveFIFO interface when FPGA is configured successfully*/ if (glConfigDone) { CyU3PDebugPrint (4, "\r\tSwitch to slaveFIFO interface.\r\n"); CyU3PEventSet(&glFxConfigFpgaAppEvent, CY_FX_CONFIGFPGAAPP_SW_TO_SLFIFO_EVENT, CYU3P_EVENT_OR); } isHandled = CyTrue; } } |
As I understand, this is the part that is called when recieving the B1 command in order to change to slave FIFO mode. As the documentation says:
"The FPGA Configuration Utility sends the vendor command 0xB1 (VND_CMD_SLAVESER_CFGSTAT) automatically after all the configuration data has been sent to FX3."
However, this messages ("\r\tVND_CMD_SLAVESER_CFGSTAT\r\n" and "\r\tSwitch to slaveFIFO interface.\r\n") are only printed with the case that is not working!
When it works this messages are not printed.
Some questions:
- Why does the PID changes if the FPGA was already powered on when I connect the FX3?
- Is it possible to fix this issue and make the programming work? I have a board that will have FX3 device integrated and both the FPGA and FX3 will be powered at the same time so I don't want to risk it not working.
Thank you.
Show LessThe UAC example in FX3 SDK reads audio data from the SPI flash.
I need to use the SlaveFIFO interface to input audio data to FX3.
Is there an FX3 example or project for UAC with SlaveFIFO?
Thanks!
Show LessOn the USB3.0 interface of the CY3014 (FX3), we see some deviations on the Spread Spectrum (SSC) 5GHz when comparing to the USB3.0 standard. The standard prescribes min.-5300ppm/-3700ppm and max.300ppm. USB PHY tests made at external digital testing lab, shows that the SCC is unstable and out of USB range (-5400ppm and 500ppm). We are using the recommended ASEMB-26.000MHZ-LY-T (10ppm) oscillator. What could be wrong? All other USB3.0 tests passes...
Show LessHello,
I have two FX3 chips in a JTAG chain connected to OpenOCD. I use FT2232H module and OpenOCD 0.10.0. Cypress SDK 1.3.4.
...\OpenOCD-20181130\bin>openocd -f myftdi.cfg -f board.cfg
Open On-Chip Debugger 0.10.0 (2018-11-30) [https://github.com/sysprogs/openocd]
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
trst_only separate trst_push_pull
jtag_ntrst_assert_width: 200
jtag_ntrst_delay: 200
RCLK - adaptive
adapter speed: 8000 kHz
fx3_1.cpu
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : clock speed 8000 kHz
Info : JTAG tap: fx3_0.cpu tap/device found: 0x07926069 (mfg: 0x034 (Cypress), part: 0x7926, ver: 0x0)
Info : JTAG tap: fx3_1.cpu tap/device found: 0x07926069 (mfg: 0x034 (Cypress), part: 0x7926, ver: 0x0)
Info : Embedded ICE version 6
Info : fx3_0.cpu: hardware has 2 breakpoint/watchpoint units
Info : Embedded ICE version 6
Info : fx3_1.cpu: hardware has 2 breakpoint/watchpoint units
Info : Listening on port 3333 for gdb connections
Info : Listening on port 3334 for gdb connections
As you can see we have two ports 3333 and 3334 for gdb connection. I can debug first FX3 at 3333 port without any errors at all. But I can't access second FX3 at 3334.
OpenOCD hangs. I'm sure there is no signal integrity troubles at JTAG lines. Configuration files are attached.
Regards
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