USB superspeed peripherals Forum Discussions
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I have been investigating and managed to make this configuration work:
Camera: RAW8, 1638x1232
MIPI Block: RGB565_2, 819 hResolution
GPIF: 16 bits
Probe Control: 1638x1234 B
UVC: 819x1234, 16bpp
The idea is for the GPIF to receive 2 bytes in every cycle, and then send the information to the PC with 2 bytes per "pixel", so we get a picture with half the columns.
The next step would be to make something similar, but with a 24b GPIF bus, so 3 bytes are sent to the GPIF block every cycle. The UVC and Probe Control don't need to be modified if I understand correctly. MIPI block should be set to RGB888 and 546 hResolution, and GPIF to 24b. The whole configuration is shown below:
Camera: RAW8, 1638x1232
MIPI Block: RGB888, 546 hResolution
GPIF: 24 bits
Probe Control: 1638x1234 B
UVC: 819x1234, 16bpp
But when I set the GPIF bus to 24b it doesn't work. I even changed the second parameter of CyU3PMipicsiGpifLoad to 0x5FD0 so it is multiple of 3, as specified in the CX3 TRM. I know it doesn't work because I output (via COM port) the number of bytes received through the DMA, and it shows 0 DMA callbacks with type CY_U3P_DMA_CB_PROD_EVENT.
The information input into the Cypress MIPI Configuration Tool is:
THS-Prepare: 60
THS-Zero: 250
Input video format: RAW8
Output video format: 24-bit
Data lanes: 4
CSI Clock: 480MHz
H-Active: 1638
H-Blanking: 1810
V-Active: 1232
V-Blanking: 50
Frame rate: 45
This tool confirms that the configuration of the MIPI block is correct:
CyU3PMipicsiCfg_t cfgUvcFullFOVx2Mipi4Raw8 = {
CY_U3P_CSI_DF_RGB888, /* dataFormat */
4, /* numDataLanes */
1, /* pllPrd */
82, /* pllFbd */
CY_U3P_CSI_PLL_FRS_500_1000M, /* pllFrs */
CY_U3P_CSI_PLL_CLK_DIV_8, /* csiRxClkDiv */
CY_U3P_CSI_PLL_CLK_DIV_8, /* parClkDiv */
0, /* mclkCtl */
CY_U3P_CSI_PLL_CLK_DIV_2, /* mClkRefDiv */
546, /* hResolution */
0 /* fifoDelay */
};
Is there something wrong or something I need to take into consideration?
How can I make it work with 24 bits?
Show LessHi Cypress,
I want to connect my ic and Cypress fx3 by GPIFII, my ic is GPIFII master, fx3 is slave.
I modified UVC firmware of AN75775 as uvc.7z.
I modified cyfx by gpif tool, I set I/O matrix configuration in accordance with my requirement, but I don't modify state machine, I don't know how to design it, it looks very complex.
After modifying, my fx3 couldn't receive any data, my cyfx file and cyfxgpif2config.h in the fx3_uvc.cydsn.7z, could you check or modify it ?
Thanks.
Show LessI'm working on a consulting project that needs a Composite HID + Bulk device. I have many years of HID experience, being the author of HIDmaker software for Microchip devices, but I am completely new to Cypress FX3 devices and framework.
I am set up & able to compile & run stock FX3 demos, especially the HID "mouse in a circle" and BulkSrcSink demos on the SuperSpeed Explorer Kit board. I am able to capture HIgh Speed bus traffic with a Beagle 480 analyzer.
The trouble came in when I tried to make a Composite device by merging code from the Cypress cyfx3_hid demo into the cyfxbulksrcsink demo, to make a single project that contains both a Bulk Interface and a HID Interface.
I chose to use two separate threads in my merged project : one for the Bulk Interface, and the other for the HID Interface. (I have one CyFxApplicationDefine() function that calls 2 routines that create a thread for the Bulk Interface and another thread for the HID Interface. ) As I am new to FX3, I don't know if trying to use 2 threads like this was a good idea or not. I would appreciate any feedback you would care to share on that subject.
I have added many CyU3PDebugPrint() statements, to tell me which routines get called. I have tried running with both threads being created, or only one of these 2 threads being created.
I believe that I have merged the Descriptors together correctly, and have gotten the project to compile without errors, but at run time, the merged project fails in the very beginning of the run, during the bus speed negotiation phase. Here is a screen shot of a Beagle capture of the merged project with only the HID thread enabled:
You can see that in both attempts at bus speed negotiations, the device times out and suspends, but the second suspend (Index 15) is total -- the PC doesn't make any further attempt to communicate with the device. Notice the details of the Chirps in the two attempts.
By contrast, here is the beginning of a capture of the working cyfxbulksrcsink project:
This run succeeds. Notice the details of the Chirps in the two attempts -- different than in the non-working project. Notice that after the second <Full-speed> state (Item 18), the PC immediately sends a SOF and begins communicating with the device.
So the key question is "Where in the Cypress code would this speed negotiation behavior be getting screwed up in my failing merged example ???"
Another curious thing, even about this working example, is that I was connecting this SuperSpeed - capable example to a USB3 receptacle on the Windows 10 PC through a new USB 2 hub, to force High Speed communication so the Beagle 480 could capture data. But for some reason, we wind running the whole project in Full Speed. Why is that happening ?
Since this merged project is totally non-proprietary to my client, I could certainly provide the current (non-working) source code if anybody wanted to look it over.
Any suggestions?
Best regards,
Dr Bob Miller, Trace Systems Inc.
Show LessHello,
Is there a recommended power supply circuit diagram when using fx3S with self power?
Please tell me about the processing of the VBUS and VBATT terminals.
Best Regards,
Naoaki Morimoto
Show LessHello.
I am using the AT24C256C instead of the M24M02 on the CYUSB3KIT-003 board.
In the M24M02, the eeporm works well, but I2C EEPROM Failed occurs when AT24C256C (A0, A1, A2 => NC) is used.
What settings do I need to use Microchip's 256K eeprom on the FX3?
Show Less
Hi,
We are developing a new product and found the FX3 to be a suiting alternative for our new product range.
But we are wondering about the driver options we have using this Cypress chip.
For our products we don’t have any special need for the USB drivers(just Win7/Win10), and could use the Cypress standard driver.
We don’t want to spend too much time and effort in the driver process (time to market), and cost is also an issue.
What options do we have?
• Can we distribute the Cypress driver(with Cypress VID/PID) with our products?
• Can we distribute the Cypress driver(with our own VID/PID), but what about driver signing do you have a program for that?
• ?
Regards Inge.
Show LessI have worked under product in which I required to uniquely identify each model of hardware for security purpose.
I know FX3 chip have uinque ID/die ID and we can read it from 0xE0055010 and 0xE0055014 register.
but how can we elaborate their 64-bit Hex code?
I can enhance more security to my product if each bit has some significance.
Show LessDear Sir,
We are trying to use Fx3BootAppGcc load one app image (come from EZ-USB FX3 SDK\1.3\firmware\basic_examples\cyfxbulksrcsink) to RAM,
But when cyfxbulksrcsink start up, it show the error message "CyU3PUsbStart failed to Start, Error code = 254" .
We use the "usb Control Center "download cyfxbulksrcsink to RAM by USB.
If boot the "C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\firmware\basic_examples\cyfx_rtos_example", It is OK.
Can you please tell us what causes this issues? How to fix it?
Thanks,
Martin
Show LessHi,
I am new to the FX3 and need help setting up the FX3 as a slave FIFO with an external clock. I have the superspeed kit, and I am using John Hyde's book for guidance and examples. My application ( high-speed ADC) is very close to one of his examples in the book (GPIF example 4) except for the direction of the clock.
Other than modifying it in the GPIF designer and including the new header file, do I need to make changes to the firmware?
I can probe and confirm the FX3 is not outputing any clock, but the DMA_ready flag for some reason is never asserted in this case.
How shall I approach this issue?
Thanks,
Ashraf
Show Less