USB superspeed peripherals Forum Discussions
Hello,
Is there any requirement for the SS multiplexer control signal on the FX3S. I am going to use the GPIO_38(J1).
I have two uSDcards on VIO2 and 3 respectively, they need 3.3V, so GPIO is in VIO2, that would be ok, also in my routing.
Thanks in advance...
Show Lessnow I have a project, FPGA can write data to FX3(P to U), and I want to add a U to P channel based on this project. I suppose the PC can send data to the USB, and send it to the buffer of FX3,when the buffer is full,flagc will be pulled down and FPGA will read the data from the buffer. In other word, it is a stream_out mode which is in the FX3 SDK , but i want it realize in my project(boss gives it me). According to the streamOUT source code, I choose the AUTO DMA mode and have added the state and flagc
and flagd pin in the GPIF designer. I have configure the flagc as the dedicate thread 3 and flagd water mark is 3. Endpoint and DMA channel configuration have be done But somehow when the buffer is full flagc is not be pulled down.I have attached my project.SrinathS_16
Show LessI will use two fx3 usb to communication with my devices. When I use the friendlyname to get the usb name. I only get one usb name, and I only control the newest opened usb. how to control two fx3 usb simultaneously and respectively?
Show LessCCyUSBDevice* m_pCyUSBDevice;
for (UCHAR i = 0; i < m_pCyUSBDevice->DeviceCount(); ++i){
bool isOpen = m_pCyUSBDevice->Open(i);
if (isOpen){
QString friendly_name = m_pCyUSBDevice->FriendlyName;
}
}
I implemented stream_in with CyAPI.lib. After calling WaitForXfer(), BulkInEndPtEndPt->LastError is equal to ERROR_IO_PENDING(997). I don't quite understand why this is.
TEST_METHOD(Test_StreamIn)
{
CCyUSBDevice *USBDevice = new CCyUSBDevice(NULL);
OVERLAPPED inOvLap;
inOvLap.hEvent = CreateEvent(NULL, false, false, L"CYUSB_IN");
unsigned char inBuf[128];
ZeroMemory(inBuf, 128);
unsigned char buffer[128];
LONG length = 128;
UCHAR *inContext = USBDevice->BulkInEndPt->BeginDataXfer(inBuf, length, &inOvLap);
USBDevice->BulkInEndPt->WaitForXfer(&inOvLap, 100);
USBDevice->BulkInEndPt->FinishDataXfer(inBuf, length, &inOvLap, inContext);
CloseHandle(inOvLap.hEvent);
}
#define DEBUG_PRINT_FRAME_COUNT /* Enable UART debug prints to print the frame count every end of frame */
#define USB_DEBUG_INTERFACE /* Enable custom USB interface for sensor interface debugging. */
I uer an75779 demo, but uart port is not finded in PC.
how can i do it?
thank you very much!
Show LessWe have a FX3 application that needs 120Hz pulses with varying duty cycles. For example, from 11/12 duty and 6/12 duty as the plot shown below. We may have other varying duty pulse train requirement like, 90%, 75%, 50%, 25%, 10%. Is it feasible for FX3?
Thank you in advance.
Show LessHi,
We are facing the same type of issue mentioned USB Speed change event behavior in some mother boards with "AUTO" XHCI mode configuration in BIOS and the endpoint reconfiguration for USB reset event solves this issue.
But we are working with CX3 based camera with Type-C connector.
In some motherboards boot up below is the sequence of enumeration.
- Camera connects to PC as a High Speed device.
- Host issues a reset.
- Camera comes up as Super Speed device.
In ideal condition we are establishing the USB 3.0 connection as mentioned Type C connector enumeration issue
1.This works fine in one orientation (where we will toggle the Type-C mux GPIO after a CY_U3P_USB_EVENT_SS_COMP_ENTRY or CY_U3P_USB_EVENT_USB3_LNKFAIL).
2.With the other orientation we are configuring the MUX wrongly and the device end up working as a High Speed device even after a reset from host.
To make this work we have implemented a simple logic where we will disable the USB PHY using CyU3PConnectState(CyFalse, CyFalse) and toggle the MUX GPIO again for every endpoint re-configuration process.
The problem we face in scenario 1 is we are receiving multiple reset requests during the entire boot up process and not getting connect request as USB 3.0 immediately after toggling the MUX.
Is our fix recommended and need advice if there is any other method to solve this.
Regards,
Indumathi.
Show Lesshi
CyU3PI2cPreamble_t works well if the i2c address is only 2-4 bytes width. but if the register address width is longer than 8 bytes, it is hard to use this structure.
who know how configure CyU3PI2cPreamble_t if the register length longer then 8 bytes.
for example, if i want to read register address 0x123456789acbde1234, the value with is 10byes, how to configure?
i tried to separate write/read sequence using following two functions. but cannot work seems due to clock-stretching. who can help here?
CyU3PReturnStatus_t
GW5200_SensorReadNB(uint8_t SlaveAddr, uint8_t *buf, int n)
{
CyU3PReturnStatus_t apiRetStatus=CY_U3P_SUCCESS;
CyU3PI2cPreamble_t preamble;
int i = 0;
preamble.buffer[0] = SlaveAddr;//0x21;
preamble.length = 1;
preamble.ctrlMask = 0x0000;//After the second byte,need to restart the I2C communication
apiRetStatus = CyU3PI2cReceiveBytes (&preamble, buf, n,0);
if (apiRetStatus == CY_U3P_SUCCESS)
{
IMX390_GW_delay(800);
}
else
CyU3PDebugPrint (4, "GW5200_SensorReadNB failed Error Code = %d\n",apiRetStatus);
#if 1
CyU3PDebugPrint (4, "read:");
for(i = 0; i < n; i++)
{
CyU3PDebugPrint (4, "0x%x ", buf);
}
CyU3PDebugPrint (4, "\r\n");
#endif
return apiRetStatus;
}
CyU3PReturnStatus_t
GW5200_SensorWriteNB(uint8_t SlaveAddr,uint16_t count, uint8_t *buf)
{
CyU3PReturnStatus_t apiRetStatus=CY_U3P_SUCCESS;
CyU3PI2cPreamble_t preamble;
int i = 0;
preamble.buffer[0] = SlaveAddr; /* Slave address: Write operation */
preamble.length = 1;
preamble.ctrlMask = 0x0000;
apiRetStatus = CyU3PI2cTransmitBytes (&preamble, buf, count, 0);
if (apiRetStatus == CY_U3P_SUCCESS)
{
IMX390_GW_delay(800); /* known issue for SDK I2C */
}
else
{
CyU3PDebugPrint (4, "GW5200_SensorWriteNB error!\r\n");
}
#if 0
CyU3PDebugPrint (4, "write:");
for(i = 0; i < count; i++)
{
CyU3PDebugPrint (4, "0x%x ", buf);
}
CyU3PDebugPrint (4, "\r\n");
#endif
return apiRetStatus;
}
thanks
xingxing
Hi,
we are using CX3 to get data from image sensor (ONSemi AR0330CM) + image signal processor (ONSemi AP1302) over USB to host PC. We would like to get maximum possible frame rate, but we are kinda stuck now.
We have configured all components to get 1920x1080 px, and we are able to get about 51 fps in YUV 4:2:2. In order to achieve this, we had to set THS-EXIT parameter in AP1302 to increase pause between the frames on MIPI interface. We believe that this parameter is limiting us from getting faster frame rates. We have development kit for sensor + ISP and we have verified that same settings on the kit yield same results, and reducing THS-EXIT causes fps increase.
However if we reduce THS-EXIT on our hardware, we do not get picture from the UVC interface, instead there are errors reported in MIPI error thread, namely "Unrecoverable Sync Byte Error".
I would like to understand why this happens, but I do not see any reason why there would be some pause between packets required in order to get CX3 interface working as intended. I have thought that there should be no need to any pauses or waits as CX3 MIPI received internally uses multiple threads with separate buffers and is able to switch instantly and seamlessly between the threads writing to different buffers.
Can anyone possibly explain how is THS-EXIT related other parameters and give us some hint of what we can change so we can reduce this value even further?
Thanks a lot for any ideas, hints and other pieces of information that might help us.
EDIT 04/04/2019:
After some more experimenting we have concluded that value required for THS-EXIT depends on packet size. If we increase packet size, we have to increase THS-EXIT as well. It looks like CX3 does need some time to process the data it has received into it's buffers before it can receive another packet.
Can anyone clarify if there is any strict requirement for pauses between MIPI packets, and how to calculate required pause length?
Best regards
Ivo
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