USB superspeed peripherals Forum Discussions

In Cypress USB streamer example, when I use USB control center, select bulkin endpoint, then data transfer, transfer data in, for bytes to transfer, anything that is not a multiple of 1024 will result in

BULK IN transfer

BULK IN transfer failed with Error Code:997

For my own application, I want to do register read/write via USB to FPGA device in addition to streaming large amount of data. Is it possible to read/write data in multiple of 2*int32, instead of always asking for n*1024 bytes?

If that is not possible, what's the alternative solution? Can I create another two end points, that has maximum package size set to 8 bytes?

Thanks,

I want to design a storage device using the following approach:

usb3.0 <==> fx3 or fx3s <==> fpga <==> big storage(sd-card or ssd)

My questions are:

1) What is the best selection in this case (fx3 or fx3s)? and why?

2) What best firmware example should I start with?

3) I'm aware i'll need slavefifo firmware example, which one best suits this approach (synchronous or asynchronous)?

4) How can I combine Mass Storage application with slavefifo application? any helpful example?

Thank you for your time and further coming response 

Hello,

I'm designing a new board with CYUSB3014 and a Lattice FPGA - ECP5 (I have the Lattice VIP EVK that I base my design on it).

My goal is to program the ECP5 flash via the CYUSB3014.

I have 3 questions:

     1. is Macronix MX25L3233FZNI-08G flash memory compatible with the CYUSB3014?

     2. How do i connect my SPI channel both the the ECP5 for programming and for the flash memory?

     3. Can I use the same memory for both?

Thanks,

Ofer.

@ YangyangC_06   按照你推荐的 USB Superspeed Peripherals、 USB Low-Full-High Speed Peripherals。我做了对比，对比了硬件和固件上的区别，但是没有发现问题。那我就把我正在用的工程上传给您，麻烦您帮我分析下。

Hi,

I'm using a CX UVC-CDC device that streams data from a custom sensor.

My requirement is to restart the CX3 from the Host PC.

I also don't know how to write a host side application that can send such a request. So would some help regarding that also.

How can i implement such a requirement.

Regards

Ajay

Hi,

Regarding Raid1 code example, what is the buffer that holds data transferred (To/From SD card via DMA Bulk IN/OUT) when CY_FX_MSC_SCSI_WRITE_10 & CY_FX_MSC_SCSI_READ_10 are called by the CBW?  I'm looking for the buffer in the CyFxMscApplnParseCbw() function but I couldn't find it.

Any helpful answer is appriciated

Hello.

I know UVC version of 1.5 was released recently.

Anyone have an idea What maximum UVC version FX3 can support ?

Thank you.

Hi everyone.

Could someone please help me, please.

I'm now designing data transfer from FPGA to PC via FX3 using synchronized interface.

The FPGA works as:

1. Assert SLCS/SLWR first.

2. Send 52 bytes data (Leader) with PCLK.

3. Then deassert SLCS/SLWR once.

4. Assert SLCS/SLWR again.

5. Assert PKTEND (with PCLK)

6. Deassert PKTEND/SLCS/SLWR.

7. After this, video data will be transferred with same sequence.

My GPIO is configured as shown in GPIOstatemachine.jpg.

The PC receives Leader correctly, this is good.

But the problem is, it seems the ZLP arrives after the Leader packet.

Is it correct always ZLP issued ?

Could you please let me know my GPIO design has any problems.

Thank you,