USB superspeed peripherals Forum Discussions

import project “C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\firmware\dma_examples\cyfxbulklpmanual”， can not receive debug message in function CyFxBulkLpApplnInit(), I only change to another FW, host can receive debug message.

Hello,

The code I'm using was taken directly from the synchronous slave fifo "cyfxslfifosync" example.

Besides the sync slave fifo protocol I need also to control GPIO bits from a control-transfer endpoint.

I found where/how to initialize the desired GPIO bits (done), but I have no clue how to add my code

to change GPIO bits from control endpoint.

I see the bulksrcsink example but I'm having difficulties to figure out how to integrate that with the

cyfxslfifosync code.

Please some hints, directions. Is there a more straightforward example for me to follow ?

Many thanks.

Luis C.

添付回路図のように基板を修正出来上がってきた基板でUSB BOOTで立ちあげて

Control Centerで書き込みをして、「Programming of SPI FLASH Succeeded」に確認して

基板をSPI BOOTにSWを変更して立ちあげても カメラの認識せず、USB BOOTLOADERで上がってきます。

SPIの状況を見ると、立ち上がり時にSPIの動作をしているのですが、少しで止まってしまっています。

デジアナでログを取りましたので添付します。

ROMを１個商社から聞いた実績のあるS25FS128SAに変えてみましたが状況は変わりません。

書き込んでいるイメージファイルを添付します。

以上、宜しくお願いします。

Hi All,

Can someone point me to peripheral register view. Default superspeed sdk does not show anything in peripherals tab in debug view.

Interpreting through mem dump becomes quite difficult and time consuming.

Cheers

Rohith

Hello,

SPI interface (SPI_SCK,SPI_SSN,SPI_MISO,SPI_MOSI) in fx3 works only for booting(4 bit wire interface with spi flash).I cant use these (with another CHIPSELECT )spi controller for other slave (example zynq as slave controller).

if i do this interface,fx3 booting is going to fail.

what is the reason?

Thank you.

Hi Sridhar,

I have just checked with onsemi, theAptina MT9m114 image sensor used in the AN75779 reference code is already in EOL. The latest MT9M114 eva board they have is using different interface, which mean there is no way to test out the AN75779 firmware whether can work with MT9M114. Please advise

The MT9M114 eva usd in AN75779:

https://www.ebay.com/itm/Aptina-MT9M114-55CSP-Demohead-Rev2-Board-CMOS-/283446418824

====Old Mt9m114 eva board====

The connection is similar with the Aptina interconnection board

This model already EOL

====New mt9m114 eva board======

The connection is diff with the Aptina interconnect board.

This model is still in production

I want to implement loopback that is based on slavefifosync project, but my customized fx3 hardware supports only two flags connection on pins (G7 & G6),

but loopback source code uses 4 flags (flaga, flagb, flagc & flagd). Can I make loopback source code work with only two flags (example: flaga(full flag), flagc(empty flag))?

If yes, what changes should I do in the source code and pin configuration? And what do you suggest about this approach.