Hi I am looking into using NetX with an FX3.

I cannot find any of the functions described in the NetX_User_Guide (cannot find anything that starts with nx_ )

Is there a particular header file needed to be included to access these?

I am aware ThreadX is only provided in binary form, but I would expect the API calls to be exposed to the developer in a header file or something.

Final question, is there a guide for using NetX or generally ThreadX OS services with the FX3?

Thanks,

Levi Riley

I am in the process of designing a new camera that must interface with an existing device incorporating the CX3 chip. So, the MIPI input signal lines are already defined on the connector of the existing device, and cannot be changed. Consequently, the MIPI signal lines (for routing the signals from the image sensor) on the new PCB to-be-designed must match the existing device. To achieve this, I have to swap the location of the +ve and -ve MIPI lines/traces on the PCB, which complicates the layout.

I was wondering if CX3 has the hardware functionality to allow swapping the signals of the same channel/lane so that I could choose whichever signal that facilitates easier routing to the appropriate pins/inputs. Has anyone done this before?

Thanks,

Mo

Couldn't get MT9M114 eva board

Cypress made interconnect board that is compatible for Aptina older boards and FX3 Explorer kits.

i.e. CYUSB3ACC-004 https://www.cypress.com/documentation/development-kitsboards/cyusb3acc-004-aptina-image-sensor-interconnect-board-ez-usb…

Since the new aptina boards are coming up with a different connector, we made a new interconnect board for it.

i.e. CYUSB3ACC-004A it will be available for purchase for customers on Cypress store by August 26th.

Can cypress share   some CYUSB3ACC-004A   Interconnect Board information？

Hello,

I have a very critical question,

I have an FPGA (ARTIX7 C7A100T FTG256) communicating with FX3 USB3.0 chip and from another site with a wireless chip ADC.

When I download SLAVEFIFOSYNC .img to FX3 chip, I can only get BULK OUT and get 997 error for BULK IN. I read application note for AN65974.zip where It mentioned try USBBULKSOURCESINK with powerstat function. Now I can see "BULK IN" and "BULK OUT" streaming both in control center and in streamer.

I want FIFO application to work under this power stat function. Please help me.

1) is this hardware problem or software?

2) How to fix this problem?

3) With this .img file I tried to upload bitstream to FPGA and get error that it is not possible. how to fix this?

P.S.  Linux installation is not possible for EZ USB. very vague explanation in readme file.

Thanks,

hi sirs,

    i want to config raw8 format,but here has somes error ,please help me!

CIS clk = （3840*8）*10^6/30.72/2/2 = 250MHZ ,but the tool calc result is 749.95 ?

where is error about output pixel clock ?

Hi,

I'm trying to read current value of the Complex GPIO timer (GPIO [25]) whenever i get the Strobe signal from the sensor. One of the GPIO pin (GPIO[19]) is configured as interrupt to Strobe signal. The issue here is whenever the camera exposure is changed, GPIO Interrupt is not invoked for both positive edge or negative edge of the Strobe signal. Also Interrupt is missing for only one strobe signal and after that interrupt for next strobe signal is received properly. Upon debugging I have found that CY_U3P_DMA_CB_PROD_EVENT in the DmaRead Callback function is pre-empting the GPIO Interrupt. I have tried changing the interrupt priority for USB Dma Block and GPIO block using CyU3PVicIntSetPriority(vectorNum,priority) API but this API function doesn't seems to have any effect in the interrupt priority. Please let me know whether setting priority in this API changes the priority of the interrupts.

Is there any other ways to handle priorities between Interrupts or Callback functions ?

Thanks,

Karthick S

Hello,

I found the FX3 FAQs (KBA224051), the description of BACKFLOW_DETECT in this article was as follows:

Question: In the AN75779 example, I enabled BACKFLOW_DETECT. When the FX3 Firmware calls CyU3PGpifDisable(), FX3 occasionally stops responding. Why does it happen?

Answer: It may happen because of PIB/GPIF error interrupts invoked in the application. If you enable BACKFLOW_DETECT, you need to disable any interrupt with the CyU3PVicDisableAllInterrupts() function during  the CyU3PGpifDisable() process.

I actually encountered this problem and was able to solve it with the provided workaround, but there are some questions.

In the AN75779 source code, the PIB/GPIF error interupt callback function only sets 1 to the flag.

So I don't think there is a problem with the processing.

What mechanism does FX3 stop responding to?

My application also uses UART interrupts, can I disable only PIB/GPIB error interrupts?

Please let me know if you have any information.

Regards,

Shimamura

Hi,

I am Using FX3 and the Image sensor processor OV426, The Both FX3, and the Processor are isolated by the digital isolator, 

My Doubt is Where I need to place the series resistor Near the FX3 or Processor. Because the Series resistor should be placed near to the Source. Here My Image sensor processor us a source.

Where I need to place. Near FX3 or Near to the Processor after isolator?

Hi All,

     I am designing a simple project which writes a 16 bit data and reads from my application board.

I have built custom Board using FX3 and Spartan FPGA 6.

Iam able to do the boot loading firmware.

As a firmware for FX3 using SyncSlave FIFO image.

Just modified few things : changed to 16bit Databus and Buffer count as 1 from 2.

In GPIF iam using Flagc as dedicated thread 3 for FPGA reading from FIFO.

Right now iam not writing anything into FIFO(no FPGA Logic Made).

Iam using USB Control Centre to  Data ut just 2 BYTE (16bit)  and see my FlagC is Showing after reading 2 Cycles (along with recommended latency).

But my FLAGC always in High. its not going low. Data also not coming from Buffer.

Could Somebody get me a help out this it will be gratefull.

Please.  Thank you

Rgds,

Muthu.