USB superspeed peripherals Forum Discussions
Hello,
my application really needs 2.4 Gbps capture over the D-PHY/CSI-2/GPIF/DMA chain, so I absolutely need to cope with 100 MHz capture with the GPIF.
I therefore needed to change the master clock from 384 MHz (= 19.2 MHz * 0x14) to 403.2 MHz (= 19.2 MHz x 0x15), by setting to CyTrue the setSysClk400 field of the clkCfg parameter of the CyU3PDeviceInit function call.
I'm sure that this is working, since after rising the clock speed I'm not suffering any more (silent) FIFO overflows.
Unfortunately I'm experiencing strange code instabilities (random failures of application-level tests that come and go according to apparently non-correlated changes in the CX3's FW code) in that configuration, that I manage to completely resolve in two very different ways:
1) switching back to the 384 MHz master clock (and testing using a lower rate data source)
2) keeping the instruction cache always disabled instead of enabling it at boot time
The first option is not compatible with my 2.4 Gbps requirement, so it is not a real solution, while the second option so far appears to be fine in (sustained) practice, even if quite weird from a theoretical point of view.
Considering that the CX3/FX3 Technical reference Manual seems to forbid the 403.2 MHz setting for the master clock (as a value of 0x14 is mandated for the FBDIV field of the GCTL_PLL_CFG register), I'm concerned that there is some undocumented side-effect of that configuration, possibly affecting the instruction cache functionality.
Any comment from Cypress or other users ?
Let me also ask if an intermediate master clock frequency of 400 MHz could also be obtained, by setting GCTL_PLL_CFG.REFDIV to 6 and GCTL_PLL_CFG.FBDIV to 125.
That would still be in contrast with the Technical Reference Manual and would require overriding what currently implemented in the SDK.
Thanks and best regards, Nicola.
Show LessWe built our own boards using FX3. I connected my PC and FX3 via USB, but the driver won't come up to my PC. The circuit diagram is the same because it is referenced to the EVM board. PMODE is set to USB Boot. I know that romboot is basically in there. Why can't the USB side connect? I checked the power supply. The 19.2 MHz clock does not work because the USB is not plugged in.
Show LessHello,
I am working on a John Hyde example (Bidir GPIF Slave interface from GPIF_Example6) where I have a Debug console attached to UART, and I am modifying it to copy these debug messages to EP1 IN (Bulk configuration).
I also followed some DualConsole example where an equivalent work is performed to retarget messages to I2C.
What I did is that I defined a manual DMA this way
/* DMA Definition */
// Setup and flush the endpoint
Status = CyU3PSetEpConfig(0x81, &epConfig);
// Create a AUTO channel for the Status to USB transfer, CPU detects and COMMITs the last short packet
CyU3PMemSet((uint8_t *)&dmaConfig, 0, sizeof(dmaConfig));
dmaConfig.size = CY_U3P_DEBUG_DMA_BUFFER_SIZE; // Use same size buffers for all USB Speeds
dmaConfig.count = 15;
dmaConfig.prodSckId = CY_U3P_CPU_SOCKET_PROD;
dmaConfig.consSckId = CY_U3P_UIB_SOCKET_CONS_1;
dmaConfig.dmaMode = CY_U3P_DMA_MODE_BYTE;
Status = CyU3PDmaChannelCreate(&CPU2USB_Handle, CY_U3P_DMA_TYPE_MANUAL_OUT, &dmaConfig);
Status = CyU3PUsbFlushEp(0x81);
This DMA is then used at each call to mynew DualDebugPrint function largely inspired by John Hyde DualConsole example:
CyU3PReturnStatus_t DualDebugPrint(uint8_t Priority, char* Message, ...)
{
// This takes the same parameters as CyU3PDebugPrint and my code is modeled on CyU3PDebugPrint
// I format Message, including any parameters, into a DMA Buffer then Queue this buffer for EP1 IN
// I check for Console Input after every Console Output
// A Queue timeout is used to ensure that Console Input is called at least once a second
CyU3PReturnStatus_t Status = CY_U3P_SUCCESS;
va_list argp;
CyU3PDmaBuffer_t CurrentDMABuffer;
// First do some error checking
if (Priority > glDebugTraceLevel) return CY_U3P_SUCCESS;
if (CyU3PThreadIdentify() == NULL) return CY_U3P_ERROR_INVALID_CALLER; // This function can only be called from a thread
// OK to proceed, get a buffer then use a Cypress routine to do the Message interpretation
CyU3PMutexGet(&EP1IN_DebugLock, CYU3P_WAIT_FOREVER);
// Allocate the buffer for formatting the string.
CurrentDMABuffer.buffer = CyU3PDmaBufferAlloc(CY_U3P_DEBUG_DMA_BUFFER_SIZE);
if (CurrentDMABuffer.buffer == NULL) CheckStatus("CyU3PDmaBufferAlloc", CY_U3P_ERROR_MEMORY_ERROR);
if (Status == CY_U3P_SUCCESS)
{
CurrentDMABuffer.count = CurrentDMABuffer.size = CY_U3P_DEBUG_DMA_BUFFER_SIZE;
CurrentDMABuffer.status = 0;
va_start(argp, Message);
// MyDebugSNPrint updates CurrentDMABuffer.count
Status = MyDebugSNPrint(CurrentDMABuffer.buffer, &CurrentDMABuffer.count, Message, argp);
va_end(argp);
// Increment the count to include the NULL character also.
CurrentDMABuffer.count++;
}
if (Status == CY_U3P_SUCCESS)
{
// Copy the output to the UART Console also for this dual console example
CyU3PDebugPrint(4, "%s", CurrentDMABuffer.buffer);
// Push this message to EP1 IN
Status = CyU3PDmaChannelSetupSendBuffer(&CPU2USB_Handle, &CurrentDMABuffer);
//CheckStatus("CyU3PDmaChannelSetupSendBuffer", Status);
// Wait there for DMA completion (actually a non-sense ?)
//Status = CyU3PDmaChannelWaitForCompletion(&CPU2USB_Handle, CYU3P_WAIT_FOREVER);
}
if (CurrentDMABuffer.buffer != NULL)
{
CyU3PDmaBufferFree(CurrentDMABuffer.buffer);
}
CyU3PMutexPut(&EP1IN_DebugLock);
return Status;
}
It works fine but what happens is that while UART messages are received OK, I loose frames sent to EP1 when I don't read them fast enough (via USB Control Center).
Also, looking at how loss occur, it seems that number of DMA buffers are actually lower than value configured (16 in my case).
Is there a way to make sure data are not lost within FX3 without "locking" the whole FW (eg using CyU3PDmaChannelWaitForCompletion function) and other DMAs execution ?
Thanks for help
Christophe
Show LessHello Guys,
I have actually a simple Question. Can I create for FX3 a parallel Statemachine in GPIF II? I mean like 2 starts and they do seperate things and give each other flags... . I mean FX3 has 4 threads? So Actually I Could use one for one state machine and 3 for another do I? I.E. I want to make a speaker in one statechart and mikros with 3 threads in another. So the mikros don't listen to the speaker, but to the echo?
Yes, I could do this serial, but it would be a lot easier in parallelism for me, that is why I am asking I tried, but it had an error... and i can't find any mentioning about that in manuals
Hello,
Assuming we are using another camera than the OV5640.
Assuming we are using a camera that can do RAW10 spread on 4 MIPI lanes.
The short spec of the RDK says it can handle 1080p @ 30fps but does not precise the pixel format.
Parsing docs, i have found, it might have been for YUY2 (16bits/pix)
According to the spec of the CX3, it looks like it could handle up to 2.4Gbits/s
1920x1080@60fps in RAW10 is 1.24Gbits/s, well below 2.4Gbits/s
even if it has to go by 16bits on the GPIFII bus, it would take only 1.99Gbits/s.
RAW10 could even be packed in 24 bits output format if i understand well, which would make it into 1.49Gbits/s
The highest bitrate that i found in e-con_CX3RDK_OV5640_Firmware_Package.zip/CX3RDKOV5640 Release Notes.txt
is 2592x1944@15fps in YUY2 : 1.209Gbits/s. A little bit lower, but now very far.
Then, am I right to assume that the Denebola RDK can handle the bitrate of a 1920x1080@60fps in RAW10 video stream ?
Thanks for your help.
Show LessHi Cypress,
We bought two CYUSB3KIT-003 Explorer kits and used AutoMaster<=>AutoSlave in AN87216 Designing a GPIF™ II Master Interface to transfer the data between the two kits. They are working perfectly.
Then we modified the GPIF II programs to change the 32-bit bus to 16-bus. They also work very well.
Now we use our FPGA to simulate the Slave FIFO. We can transfer the data to FPGA without any problem. However, when we tried to send the data from FPGA to AutoMaster we got nothing even though FLAGA indicated data available and it was low after the some clock cycles.
When using the two kits to transfer 8 bytes from Slave to Master, the timing diagram shows 6 clock cycles and then SLRD goes high which is correct: 2 + 8/2 = 6 cycles. Please check out the attached Master_Slave.png for details.
However, when using our FPGA to transfer 8 bytes to Master, the timing diagram shows 1024 clock cycle reads even if FLAGA goes low after 10 clock cycles (only 8 words in the FIFO) the Master is still trying to read and the PC program read 0 byte. Please see the attached Master_FPGA.png for the timing diagram.
Anybody knows what is going on here and how to solve the problem?
Show LessWe are using a CYUSB3014 in our current product, but we want a variant with USB 2.0 only.
Can we leave the SSRXP, SSRXM, SSTXP, SSTXM unconnected? Or tie to GND? Anything else to change to USB2.0 only?
Thank you!
Show LessHello,
we use the CYUSB3KIT-003 EZ-USB® FX3™ SuperSpeed Explorer Kit and have some problems with the UartLpRegMode example application (FX3 SDK 1.3.4). When we send data from the host pc to the fx3 via UART, there is a loss of data. When we send for example the string "1234567890" with 115200k Baud every 100ms, we sometimes just receive "1234" on the pc and the rest of the data is lost.
1. Are there any known issues concerning UART transfers? I think the fx3 receives the wrong data.
2. When we set the uart tx timeout to 0xFFFFFFFF CyU3PUartSetTimeout (1, 0xFFFFFFFF), the CyU3PUartTransmitBytes() function never returns. Is that ok?
Thanks in advance
Marc
Show Less