Hey,

What is the best way to update the FW on the CX3 while in SPI boot mode (USB on failure) after the 1st FW flash?
When the SPI is empty, connecting the board to the PCB will detect it as cypress FX3 USB BootLoader Device, then with the EZ-USB control center we are able to download the FW to the SPI and it works good. what will be the best procedure to update the FW form this point? we can hold the SPI flash at disable and this will invoke the USB BootLoader Device again and we can flash again but I was wondering if there is a simple way to do it with SW only.
we tried using  CyU3pUsbJumpBackToBooter() (we called this function when changing the resolution) and it did not work (see code below).

*******************************************

                   /* Request to switch control back to the boot firmware. */

                    /* Complete the control request. */

                    CyU3PUsbAckSetup ();

                    CyU3PThreadSleep (10);

                    /* Get rid of the DMA channels and EP configuration. */

                    //CyFxBulkSrcSinkApplnStop ();

                    /* De-initialize the Debug and UART modules. */

                    CyU3PDebugDeInit ();

                    CyU3PUartDeInit ();

                    /* Now jump back to the boot firmware image. */

                    CyU3PUsbSetBooterSwitch (CyTrue);

                    CyU3PUsbJumpBackToBooter (0x40078000);

                    while (1)

                        CyU3PThreadSleep (100);

                    break;

********************************************

Thanks, 

Dear cypress team,

i need to use GPIF II designer  with 24 bit data bus. but 24 bit option is not available in designer tool . can you explain why it is not available . and please give a suggestion if it is possible to use 24 bit  data bus width after the config file is generated. .

thanks and regards, 

Rakesh 

Hello, dear Infineon support community !

I am currently working on a custom UVC application based on AN75779 and CYUSB3KIT_003.

To simulate data coming from a camera sensor, an FPGA generates the signals corresponding to a 640 x 480 YUY2 video stream @15fps, 16bits/pixel, as defined in the descriptors of the original AN75779 project. (See attached Probe_FPGA_Signals.zip archive for oscilloscope probes on these signals, acquired on FX3 GPIF, and a readme.txt file with comments).

My FX3 system is recognized as a UVC device, and does appear in VLC's Capture Device interface, which is how I initiate video streams.

However, I can't seem to receive any of the input data on the host side, as shown in the following UART messages. By following this similar support thread ,  I implemented some additionnal information messages based on key flag variables, such as bufferCount which indicates the amount of data in the current DMA buffer. 

From this, I can conclude that :

• The state machine is not blocked, as the current SM state oscillates between 2 and 5 (respectively WAIT_FOR_FRAME_START_0 and _1).
• There is a stream of data at approximately 15 fps, which triggers both the prod and cons Events
• The buffers of my DMA channel remain desperately empty.

Moreover, the Wireshark traces reveal that there is an ongoing stream ; but the payloads emitted by FX3, although at a rate of ~15 /s , only contain the 12-byte header , with its second byte alternating between 0x8E and 0x8F. (See  Wireshark Trace_Header 31-08.png )

Here are the modifications I added to the original AN75779 project :

• Modifications to the GPIF configuration : 16-bit data bus, LD_ADR/DATA_COUNT limit modified to 8183, activated SPI and I2C, sampling on negative edge.
• Implementation of Extension Unit controls, using SPI and I2C protocols. 
• Additionnal flags in UART log messages

My questions are the following :

• Could you please suggest any interpretation as to why no data seems to be sampled and stored into the buffers, and maybe a solution ?
• Also, are there any expected limitations in terms of horizontal blanking ? I arbitrarily chose to wait for 160 PCLK cycles between two active LV signals, but please let me know if that's inadequate. 

I understand that the symptoms are nearly identical to the previously mentioned thread, where the solution was apparently a difference between the expected width/height values and the actual video signal dimensions. In the meantime, I will be trying to change UVC descriptors to close frame dimensions (640*483, for example) to see if that solves my issue, and follow once again the debug checklist from the appropriate KBA .

Please find attached the uvc.c, uvc.h, cyfxuvcdscr.c , fx3_uvc.cyfx and cyfxgpif2config.h files from my project, the uvc.c might refer to some custom functions or header files which I would rather not share on a public forum for IP reasons but can be commented without interfering with the overall program (See Project_Files.zip ). 

Best regards,

Enzo

We currently use FX3 for UVC application.  In road map,  SX3 is highlighted for UVC while FX3 is not. May I know the difference between FX3 and SX3? 

Thanks. 

Hi,

We have developed a custom PCB with the CYUSB3014-BZXC and we've noticed that sometimes when we connect the board to the PC using a USB 3 C to C or USB 3 A to C cable Windows fails to detect it. In such cases Windows does not make the new device connected sound nor does it report an error.

According to my coworkers this happens randomly, typically after the board has been disconnected from the PC for a long period of time. They tried disconnecting the board from the PC, discharging the onboard capacitors, and then reconnecting it to see if they could reproduce what seems to be a random issue that occurs after long periods of the board being unpowered  but they weren't able to reproduce it this way. My coworkers are using laptops that come with Intel 3.1 host controllers.

I added UART debug logging to our bootloader and yesterday I noticed something similar occur. I had been testing our bootloader and application firmware on an Apple M1 Mac Mini, then disconnected the board (left unpowered) for a while (maybe 20 minutes), and then connected it to the Intel 3.0 USB A port on my Windows 10 desktop PC. Windows did not make the new device connected noise, nor did it display any messages. Fortunately I had a USB UART connected to the board and managed to capture the USB events via the output, which were as follows:

Initializing FX3 Boot Firmware 1.10
Boot FW Event: CY_FX3_BOOT_USB_IN_SS_DISCONNECT
Boot FW Event: CY_FX3_BOOT_USB_CONNECT
Boot FW Event: CY_FX3_BOOT_USB_COMPLIANCE

We have a button attached to RESET#. I tried resetting the MCU using this button and didn't see anything different in the UART log, nor was the FX3 identified by Windows. The problem only resolved after I disconnected the board from my PC and plugged it back in. I'm not sure if this is the same issue that randomly occurs for my coworkers, as they didn't manage to capture the UART logs.

I'm not sure if this issue is caused by something in the hardware design or something in the firmware but it would be great if we could figure that out before the next PCB revision, which is about 3 weeks out.

Thanks,
Michael

对于slavefifoasync这个固件，想要在里面启用control endpoint，但是FPGA的信号线应该连接CYUSB3014的哪个引脚？

另外，请问在slavefifoasync这个固件中如何增加control endpoint的功能。

Hi, 

I'm using FX3S as a USB host controller. and I wanted to implement SDIO IO peripheral, I'm able to do SDIO initialization successfully. After that I'm not getting card detect event.

without card detect event If I try to query the device status (CyU3PSibQueryDevice), it is returning error status 0x68(CY_U3P_ERROR_INVALID_DEV).

I wanted to know what is the reason for not getting the card detect event. and is it possible to continue without card detect event. If yes, how?

Thanks & Regards

Yamuna G

Hello!

We are using the FX3 and the AN75779 in a customer camera project.
For certain use cases we see the code executing gets stuck on the call to CyU3PGpifDisable(CyTrue).
It hangs until the watchdog expires and the processor is restarted.
We have noted this thread:
https://community.infineon.com/t5/USB-superspeed-peripherals/About-UVC-application-backflow-detect-process/td-p/31884
We have tried the various suggestions in that thread on temporarily disabling either all or specific interrupts, but it has no effect.

Is there a known solution to this problem?

This typically happens after a commit buffer failure when the streaming is first stopped an then restarted.

Regards,

Magnus

Hi, We having trouble to receive frame when send two Frame Request two endpoint simultaneously. We are using window10 64x, CyAPI library.

I am connecting HX3PD EVP board to two FX3

DS4 to FX3_1

DS5 to FX3_2

we set device count 1, endpoint1 to be FX3_1

then device count 2, endpoint2 to be FX3_2

1.) The code below Works, however this is not our use case. We are required to send two Frame request from two different endpoint then only received two data from two different endpoint

Send first frame request using endpoint1 then receive using endpoint1

Send 2nd frame request using endpoint2 then receive using endpoint2
succeedsendA = true
succeedsendB  = true
succeedReceivedA = true
succeedReceivedB = true

2.) Our Actual use case: The code below result be

succeedsendA = true
succeedsendB  = true
succeedReceivedA = true
succeedReceivedB = false

3.) The code below result be

succeedsendA = true
succeedsendB  = true
succeedReceivedA = true
succeedReceivedB = false

We tried with different combination, it always result "endPointX->XferData(VideobufferX[currentFrame], rLenX)" will only succeed get data if it is placed before ControlEndPointExecuteCommand();

May i know how can i send two Frame request with endpoint1 and endpoint2 then only receive the data of either endpoint1 and endpoint2 simultaneously?

Thanks

Attached the ControlEndPointExecuteCommand() as reference