USB superspeed peripherals

Hi I am using FX3 USB superspeed hardware. I am trying to do file transfer from Master to Slave using cyusb_linux application. I have downloaded the latest application from your website. My OS is Ubuntu. I am getting the below errors LIBUSB_ERROR_TIMEOUT ,  LIBUSB_ERROR_OTHER and unable to clear halt data pipe. I want to transfer bulk files from master to slave. Kindly help me out in this. I have attached the screen shot. Thanks in advance.

Is it possible to change DMA configuration while running and restart DMA?

Below is a source that runs in 2-socket GPIF mode and runs fine.

and I want to stop GPIF and run it in loopback mode .

but it stop running.
The red source seems to be wrong.
Please give me guide line. Thank you.

dmaCfg.size = (usbSpeed == CY_U3P_SUPER_SPEED) ?(size * CY_FX_EP_BURST_LENGTH ) : (size);

dmaCfg.count = 4;
dmaCfg.validSckCount = 2;
dmaCfg.dmaMode = CY_U3P_DMA_MODE_BYTE;
dmaCfg.cb = NULL;
dmaCfg.notification = 0;

dmaCfg.prodSckId[0] = CY_U3P_PIB_SOCKET_0;
dmaCfg.prodSckId[1] = CY_U3P_PIB_SOCKET_1;
dmaCfg.consSckId[0] = CY_FX_EP_CONSUMER_SOCKET;

apiRetStatus = CyU3PDmaMultiChannelCreate (&glChHandleBulkSrc, CY_U3P_DMA_TYPE_AUTO_MANY_TO_ONE, &dmaCfg);
apiRetStatus = CyU3PDmaChannelSetXfer (&glChHandleBulkSrc, CY_FX_BULKSRCSINK_DMA_TX_SIZE);

( Runnig Well)

(change to loop back mode)

dmaCfg.prodSckId[0] = CY_U3P_CPU_SOCKET_PROD;
dmaCfg.prodSckId[1] = CY_U3P_CPU_SOCKET_PROD;// duplicate ?
dmaCfg.consSckId[0] = CY_FX_EP_CONSUMER_SOCKET;

dmaCfg.cb = CyFxBulkSrcSinkDmaCallback;
dmaCfg.notification = CY_U3P_DMA_CB_CONS_EVENT;

CyU3PGpifDisable(CyTrue);
CyU3PDmaMultiChannelAbort(&glChHandleBulkSrc);

apiRetStatus = CyU3PDmaMultiChannelCreate (&glChHandleBulkSrc, CY_U3P_DMA_TYPE_AUTO_MANY_TO_ONE, &dmaCfg);
apiRetStatus = CyU3PDmaChannelSetXfer (&glChHandleBulkSrc, CY_FX_BULKSRCSINK_DMA_TX_SIZE);

( running is stop)

Hi All, 

I am using a custom board where Fx3 USB controller is connected to Xilinx FPGA.
I am trying to create an board level Vhdl/Verilog test bench where Fpga is instantiated as DUT component and
FX3 as a test peripheral component.

Is there any VHDL/Verilog simulation model available for Fx3 USB Controller?

Thanks in advance,

Panneer Raja Vajravelu.

Hi,

For my initial evaluation of USB3 Vision, I am using the source code shared in the forum. Using that source code, I am able to enumerate the device as a USB3 Vision device, but I cannot connect to any GenICAM application to test the streaming. Any guidance on this would be appreciated.

Thanks in Advance,

Vigneshkumar R.

Hello all, 

Most of the data I'm trying to transmit seems to be going between the FX3 and the other chip just fine, but I'm periodically getting zero length packets seemingly coming from nowhere. I've been trying to debug this, but everything I've tried has been a dead end so far.

I'm trying to use the FX3 to connect an 8051 on our board with a host application on a windows PC. My setup is as follows:

• An 8051 that has the microcontroller business logic. 
  • It receives input from the host from GPIF-II addresses 1 (buffered) and 2 (immediate), sends responses on 3, and there's logging macros that use address 4.
  • It's mostly legacy code, except what I've changed to make it work with the FX3.
• The FX3 that's mainly passing data between the host and the 8051
  • I'm using the GPIF-II interface. The state machine I'm using is basically the async slave fifo interface provided as a sample, except that I've changed some of the pin numbers.
  • USB addresses 2, 4, 6, and 8 are connected to GPIF-II addresses 1, 2, 3, and 4 respectively.
  • I have an additional USB endpoint 10 that I'm using for debugging. Every time data a packet is added to one of the other buffers, I sent the contents and a little metadata to the host. This way, I can debug problems between the FX3 and the 8051 independent of the production app running on the host.
• On the Windows Host PC, I have the production app that's trying to use endpoints 2, 4, 6, and 8 to talk to the 8051. There's some other issues there that I still need to investigate, but it's at least able to consume data from the buffer so they never get too full.
• Also on the windows PC, there's a logger app that connects to endpoint 10, and formats and prints the packets that the FX3 has received from the 8051.

Now the problem I'm seeing is that, the 8051 sends a keepalive signal periodically to the host app, and every once in a while, we get a zero length packet as well.

Here's what I've tried in my investigation:

• I've set breakpoints in the 8051 code to check if the actual data we tell it to send really is zero, and it never gets triggered, so I can be sure that we don't ever try to send a ZLP. I've verified that the pins I'm using to communicate with the 8051 are only touched in the 4 read and write functions that I expect them to, so the breakpoints I mentioned should cover every situation.
• I've verified that the order in which the pins change to control the state machine is correct. That is to say to write to the buffer:
  1. SLWR = 0
  2. Write Data
  3. if this is not the last byte, SLWR=1 and go back to 1.
  4. If this is the last byte:
  5. PKTEND = 0
  6. SLWR = 1
  7. PKTEND = 1
• My coworker who designed the board suggested that timing issues could mean the state machine is in a different state than I thought it was, so I've done the following to check timing:
  • In the FX3 manual, it says the GPIF-II "Enables interface frequencies up to 100 MHz", which I assume means that it can change state at least once every 10ns. In the state machine, changing a single pin causes at most 3 state changes before it reaches a stable state, so I tried adding a 30ns delay after every time we change a pin. Then when that didn't make a difference, I added another 30ns just in case, but still no dice.
  • Then I tried adding a full 1ms delay for good measure after every time I changed a pin, which changed nothing either. I figured this would cover my bases if I was mistaken about how fast the state machine transitions.

I suspected that maybe there's noise or something changing the PKTEND pin long enough to trick the state machine into sending a ZLP, but my coworker has already dismissed that notion. He's the hardware guy, so I can't really make him check it, and he didn't leave a way to attach a scope or anything to the pin, so wouldn't be easy.

If anyone has any suggestions of what might be going wrong, or ideas for other things I could test, I'd love to hear them.

I have implemented a U3V camera with FX3014, but the CMOS sensor has DVP parallel interface. In order to use MIPI or LVDS CIS with high resolution, I plan to take FPGA to be a bridge from CMOS sensor to FX3014. where to find a similar project to it? it is enough even it is a UVC solution, I can study it for my design.

I am familiar with AN75779 for UVC, and I have review the doc AN65974, in which a solution with FX3 Slave FIFO is described, but it has not CMOS sensor interface besides transfer packets to FX3;  in the post"UVC Firmware for FX3 FPGA Industrial Camera Demo Kit - KBA229407", it is a introduce about UVC demo without source code disclosure. It has little help for me to design a camera.

Hi,

I am working with a sensor at 1280x720@30fps YUV422_8 output, I want to use 24bit-bus to transfer data. But when I set up this project, I found there was data padded to the frame, and I can't preview the frame directly by Amcap. I understand it is because the line size can't be divided by 24bit, then there is data padding. So I want to know how the data is padded to each frame, and how to get rid of the padded data on each frame?