USB superspeed peripherals Forum Discussions

CYUSB301X is in 32bit mode.

The questions about the interface that is supported in 32bit mode.

Is it possible to use GPIO53 ~ GPIO56 SPI mode in 32bit mode?

And is it possible to use GPIO50 ~ GPIO52 GPIO mode in 32bit mode?

Or it is set to only accept 32bit mode? (Only use to GPIO50 ~ GPIO52 : I2S / GPIO53 ~ GPIO56 : SPI)

I would like to check the GPIO dependence in 32bit mode.

Hi,

I'm using Cypress FX3 DVK in my design and CyUSB DLLs are used for USB communication.

For sending data from host to device bulk out transfer will be used and bulk in for receive data to the host.

some times bulk in transfer returns empty buffer. When I check for USB logger bulk out command is sent out and the respective bulk in data also received as a valid buffer all the time but in my application layer, I am getting as an empty buffer. If some delay is added between write and read function I am getting data properly to the application but it is not consistent. The below image is the sample code let me know if I'm missing something.

Hello everyone,

i have two questions regarding the application examples for the Cypress FX3S.

The first question is for the FX3SMassStorage example, CyFxMscApplnSibCB function:

In the same function, two kind of errors are managed by resetting the DMA Channels. But glCmdDirection is used to reset different channels:

First case:

    if (evt == CY_U3P_SIB_EVENT_XFER_CPLT)
    {
        if (status != CY_U3P_SUCCESS)
        {
            glMscCmdStatus     = 1;
            glSensePtr[portId] = CY_FX_MSC_SENSE_CRC_ERROR;
            /* Transfer has failed. Reset the DMA channel. */
            if (glCmdDirection)
            {
                CyU3PDmaSocketGetConfig ((uint16_t)(CY_U3P_UIB_SOCKET_CONS_0 | CY_FX_MSC_EP_BULK_IN_SOCKET),
                        &sockConf);
                glMscResidue -= sockConf.xferCount;
                CyU3PDmaChannelReset (&glChHandleMscIn);    // <-- resets the bulk_in channel
            }
            else
            {
                CyU3PDmaSocketGetConfig ((uint16_t)(CY_U3P_UIB_SOCKET_PROD_0 + CY_FX_MSC_EP_BULK_OUT_SOCKET),
                        &sockConf);
                glMscResidue -= sockConf.xferCount;
                CyU3PDmaChannelReset (&glChHandleMscOut);   // <-- resets the bulk_out channel
            }
        }
   }

Second case:

    if ((evt == CY_U3P_SIB_EVENT_DATA_ERROR) || (evt == CY_U3P_SIB_EVENT_ABORT))
    {
        /* Transfer has failed. Reset the DMA channel. */
        if (glCmdDirection)
        {
            CyU3PDmaChannelReset ((CyU3PDmaChannel *) &glChHandleMscOut); // <-- resets the bulk_out channel
        }
        else
        {
            CyU3PDmaChannelReset ((CyU3PDmaChannel *) &glChHandleMscIn);  // <-- resets the bulk_in channel
        }
        /* Make sure the request is aborted and that the controller is reset. */
        CyU3PSibAbortRequest (portId);
    }

Why is it different?

---------------

Second question, regarding the RAID1 application note example (AN89661):

Analyzing the content of the CyFxMscApplnSibCB function, I have found different behavior on error conditions:

if (evt == CY_U3P_SIB_EVENT_XFER_CPLT) {
    glSPortPending &= ~(1 << portId);
    if (status != CY_U3P_SUCCESS) {
      
 ...
      /* Transfer has failed. Reset the DMA channel. */
      if (glCmdDirection) {
        CyU3PDmaSocketGetConfig((uint16_t)(CY_U3P_UIB_SOCKET_CONS_0 | CY_FX_MSC_EP_BULK_IN_SOCKET), &sockConf);
        glMscResidue -= sockConf.xferCount;
        if (glRaidMultiChannelValid)
          CyU3PDmaMultiChannelReset((CyU3PDmaMultiChannel *)&glChHandleUSBOut);
        else
          CyU3PDmaChannelReset(&glChHandleWrErrIn);
      } else {
        CyU3PDmaSocketGetConfig((uint16_t)(CY_U3P_UIB_SOCKET_PROD_0 + CY_FX_MSC_EP_BULK_OUT_SOCKET), &sockConf);
        glMscResidue -= sockConf.xferCount;
        CyU3PDmaMultiChannelReset(&glChHandleUSBOut);
      }
    }

Regardless of glCmdDirection, the glChHandleUSBOut is reset. This example differs from FX3SMassStorage (the first code excerpt). Could this be a bug?

I hope this post is clear enough. Thanks in advance for you time!
Salvatore.

Hello,

I am using streamer application to transfer data from P-Port to S0-Port.But problem is that all the data transfers are failing even though I am getting PROD events.

Regards,

Sai Kumar.

Hello All,

I'm using Ez-USB suite V1.3.4.

In the attached Properties window, if I Change

configuration: Debug[active] to --> profile release / Release and

optimization level : None(-O0) to--> any other option n drop down.

Will these configurations break anything, Is it recommended to alter these changes ?

I need to optimize my code, now even if I add a single function with a single switch case and with one/two variables code size is increasing more than 2k which is unexpected. At present my code size is 167k.

So If I alter the above said options will it affect anything?

How(in what way) and where are these option will be used?

What are the recommended settings for compiler to optimize the code size?

Thanks and Regards,

Pranay.

Table 5 listed combinations of burst length, buffer size and no of buffers to give different throughputs.

How to modify cyfxbulksrcsink.h parameters to simulate these cases using FX3 SuperSpeed Explorer Kit?

CY_FX_EP_BURST_LENGTH = burst length?

CY_FX_BULKSRCSINK_DMA_BUF_COUNT = no of buffers?

How about buffer size, which parameter to be modified?

As for Table 6 for Isochronous transfer,

CY_FX_ISO_BURST = burst length?

CY_FX_ISO_PKTS = iso-packets?

CY_FX_ISOSRCSINK_DMA_BUF_COUNT = no of buffers?

How about buffer size, which parameter to be modified?

Hi All:

I'm confused for that.

According to USB spec:

Q1: If I set the U1 latency to 0x00, it means that the FX3 will resume from U1 to U0 by 0us?

Q2: If the FX3 needs 2us to resume from U1 to U0. And I set the U1 latency to 0x05. The actual time spent is 2us?

Q3: If the FX3 needs 3us to resume from U1 to U0. What happen if I set the U1 latency to 0x0?

Thanks a lot!

1). If we want to apply this chip between “CAM sensor” & “Android-10 cell phone platform”, can you help me check
whether it’s feasible design through USB “UVC” class.

2). Do you have support android side UVC driver..?

3) CX3 UVC driver can support X86 system..?? How about Android os..?

I want to extend the USB3 data with external PHY to PIPE chip connected to fpga and back.

I wanted to work with the TUSB1310A. this TI chip that can be configured as a upstream or downstream port of usb3 hub to pipe but its defined by TI as NRND (not recommended for new design)

do you know if there is another solution for this?