USB superspeed peripherals Forum Discussions
In AN87216, is Fig.5 and Fig.6 for generic example for read/write of slave, or the exact timing in the Master/Slave setup?
In the master state machine, WR and CS are asserted at the same state, this is different than Fig.6, in which WR is asserted 1 clock later after CS.
In the master state machine, in the state WR_FLAG, why is CS delayed and WR early? Will this make WR asserted before CS?
And I'm not sure why there is choice of early(2 cycle) and delayed(3cycle) here, does this mean there is pipeline between the state machine output and the IO pad? For 100Mhz pipeline should not be needed.
I need to add another two state machine chains to implement 2 RX and 2TX thread, can't proceed until it is clear how to set early and delayed.
Show LessHi
I am trying to use FX3 SDK to enable Super Speed mode of OV5640 YUV Preview running.
It seems configure CX3 to Super Speed mode in App Init method. But CX3 becomes full speed. hence only VGA is available in my custom CX3 board.
I supposed my PCB has some layout design issue regarding USB 3.1 super speed enabled.
How about CX3 Demokit? No issue from Super-speed enabling ?
Thanks.
Best Regards,
JK Cha
Show LessWhen multiple state transition path's condition are met, how does GPIF engine choose the next state?
For example, in the Master/Slave example in AN87216, in the master's state machine, if both master to slave data and slave to master data in valid, will RD_WR_IDLE go to WR_FLAG or DR_ADDR?
Show LessIn master GPIF project:
FLAGA is set to active high. This is confusing since in the state machine, the transition logic is based on FLAGA or !FLAGA, not FLAGA_Active or !FLAGA_Active, then does it matter FLAGA is set to "active high" or "active low" in master?
A possible explaination si that in the state machine's transition conditions, "FLAGA" means "FLAGA is active" and "!FLAGA" means "FLAGA is not active"? Then if FLAGA is set to active low in master GPIF project, "FLAGA" in transition conditions will means GPIO_21=low and "!FLAGA" will mean GPIO_21=high?
Is that right?
Show LessIn AN87216 examples,
CY_FX_CONSUMER_USB_SOCKET=CY_U3P_UIB_SOCKET_CONS_1 and CY_FX_PRODUCER_USB_SOCKET=CY_U3P_UIB_SOCKET_PROD_1 is used.
What decides how CY_U3P_UIB_SOCKET_... is mapped to endpoints in the firmware? Is there a static mappint relation? Where is the documentation about this?
Show LessWill GPIF control signals be dis-asserted when the state machine proceed from a state that assert that signal to a state that doesn't mention that signal? Doesn't the signal needed to be dis-asserted in the next state?
Show LessIs it possible to get MIPI output from an FX3 so that it can function as a USB3 to MIPI bridge? I want to write images (bitmaps for example) over USB3 to MIPI format to emulate a camera. Thanks!
Show LessHello,
I edited my project using the steps described in KBA225062 to enable brightness control, but the brightness slider does not appear in camera controls of any of the video tools (Amcap, MPC-HC, ecamview). All sliders are grayed out.
Any suggestions how to get the slider to appear?
Show Less
In AN87216 FLAGC is "Thread_1_DMA_WaterMark", is it really used in the state machine?