USB superspeed peripherals Forum Discussions

I  ported the AN65974\FPGA Source files\fx3_slaveFIFO2b_altera\fpga_streamIN design to an Altera EP3C5 board that my Superspeed Explorer card mounts to.

Using the sync_slave_fifo_2bit.cyfx example GPIF state machine with the cyfxslfifosync example firmware and my FPGA-generated PCLK of 80MHz, the set up works

fine with USBControlCenter.

But I have some DAQ in my eventual application that wants to lollygag along at 40MHz. Reprogramming the 3C5 for 40MHz PCLK, I am unable to find a combination of clockConfig.mmioClkDiv, pibClock.clkdiv, gpifclkdiv, clockConfig.dmaClkDiv, and clockConfig.cpuClkDiv that works with the example firmware&GPIF setup. In some instances the logic analyzer captures a "runt" frame on the FIFO interface on download of the firmware followed by ...nothing. In other cases, the interface is simply dead

(Always using USBControlCenter data transfers to tickle the FX3).

What method is there to successfully using a lower speed clock on the FX3 Explorer sync slave FIFO interface?

Hi,

I am facing an issue while reading the register of the OV5640 Camera sensor (I2C slave device in my setup) from firmware with "CyU3PI2cReceiveBytes" API through I2C. However, The camera module is working fine as I am able to stream it from Windows Host.

CyU3PI2cReceiveBytes returns CY_U3P_ERROR_FAILURE. I have further debugged the issue with "CyU3PI2cGetErrorCode" and it returns CY_U3P_I2C_ERROR_NAK_BYTE_0. Please find the code snippet below,

Hi Cypress Support,

We are refer to Asyn Slave fifo AN65974 , to use two DMA Thread to transfer data with FPGA then forward the data to USB.

But after some time, I see CyU3PDmaMultiChannelCommitBuffer(...) get error code (0x47) = CY_U3P_ERROR_INVALID_SEQUENC.

Then The FPGA still check the status of FLAGA and FLAGB  is Low.

I also attach the GPIF design file and my application code.

What's the reason lead to the issues?

Thanks,

Martin

Hi Sir,

Does CY have a USB3.0 to SATA interface bridge chip? Can you recommend it?

Thanks

Hello support,

I try to add  "CyU3PDebugPrint (4, "CyU3PDmaChannelGetBuffer buf_p.size %d\n", buf_p.size);" into CyFxBulkSrcSinkDmaCallback (cyfxbulksrcsink.c  line 227).

then streamer tools can not get data from IN endpoint.

By My understand, it maybe get very slow transfer data speed.

Can you let me know what is reason on the issues?

for your reference, I also attach my modified code on the offical sample code USBBulkSourceSink.

Thanks,

Martin

目前我們使用Cypress, CX3的板子時，有使用自有程式讀寫SPI FlashROM的需求。

想請問Cypress是否有提供相關的API可供呼叫使用？

平台環境 ：windows 7/10 x64, VS2013 C/C++

Hello,

I have been following steps as RashiV_61 mention in my last discussion (https://community.cypress.com/message/227908?et=watches.email.thread#227908 )

and when i change the endpoint type from "CY_U3P_USB_EP_BULK" to "CY_U3P_USB_EP_ISO" i got error massage after programming board i got error from windows (unknown device (Invalid Configuration Descriptor))

I use SyncADMux project from GPIF Desginder and as per firmware I use is AN65974.

I attached project file (file that has been changed are cyfxslfifousbdscr.c - to change descriptors and cyfxslfifosync.c - after changing this file (the first file was left as it was in example) I did not encounter this error)

Can FX3 support superspeed mode that has HID interface plus bulk interface?

The single HID interface mouse+keyboard example doesn't enumerate as super speed. Can it enumerate as super speed?

Good day!

( Sensor AR0341 4lane 640*480*60fps)

I didn't use your program(from sdk) before. Now I am corrected

I also have a problem with your Linux Studio

1. the CS3 Receiver Configuration tab Is not saved, which means that you need to type everything again every time. see err2.jpg

2. it is not Clear how CS3 MAPI Interface Configuration H_Active is considered as it changes only when PCLK and format are changed. Can you describe it ?

3. my sensor was configured for CPU Clock 192MHz 640*480*60fps 4 lane and an error occurred

Max Output pixel clock cannot transfer CSIData.... see err1.jpg

And I don't understand why: (

Sensor Transmitter CASE Clock 192MHz = 384 Mbps per lane

CS3 PCLK= 87,88MHz RAW10 GPIF16bit. CS3 Recover Data_Rate = 87,88* 10(PixelDepth) = 878,8 Mbps perlane.

4. And still it is unclear opposite Output Pixel Clock the error "Minimum value 301.23" is shown as it so counted ?

At the moment, the project is configured as follows:

I. Sensor AR0341:                                                                                                    CX3:

* ignore the name sensor ar0341

  CyU3PMipicsiCfg_t OV4689_RAW10_640_480_60 = 

{

CY_U3P_CSI_DF_RAW10, /* CyU3PMipicsiDataFormat_t dataFormat */

4, /* uint8_t numDataLanes */

1, /* uint8_t pllPrd */

62, /* uint16_t pllFbd */

CY_U3P_CSI_PLL_FRS_250_500M, /* CyU3PMipicsiPllClkFrs_t pllFrs */

CY_U3P_CSI_PLL_CLK_DIV_4, /* CyU3PMipicsiPllClkDiv_t csiRxClkDiv */

CY_U3P_CSI_PLL_CLK_DIV_4, /* CyU3PMipicsiPllClkDiv_t parClkDiv */

0, /* uint16_t mClkCtl */

CY_U3P_CSI_PLL_CLK_DIV_2, /* CyU3PMipicsiPllClkDiv_t mClkRefDiv */

640, /* uint16_t hResolution */

0 /* uint16_t fifoDelay */

};

status = CyU3PMipicsiSetPhyTimeDelay(1, 8);

USB works in HS mode. The reset timer is enabled.

Problems:

1 Getting multiple bundles of data CX3 freezes.

Here is a screenshot showing the logs and the location when it was frozen.

When the DMA freezes MIPI continues to work

Here is hsync (yellow) datalane0 (Red) hsync.jpg

Here is Vsync (yellow) datalane0 (Red) vsync.jpg

Here is pclk (yellow) data band 0 (Red) pclk.jpg

Did I set the values correctly?

1280 * 720 @30fps , 4lane, RAW12

CSI clock  : 448Mhz

Data Lane : 4 LANE

THS-Prepare : 70

THS-Zero : 170

Frame rate : 30fps

H-Active : 1280

H-Blanking : 1256

V-Active : 720

V-Blanking : 16

Data format : RAW12

1. Can csi clock be over 400Mhz at 4 lane?

2. CX3 MIPI Reciver Configuration default value is O.K?

/* null_RAW12_Resolution0 :  */

CyU3PMipicsiCfg_t null_RAW12_Resolution0 = 

{

    CY_U3P_CSI_DF_RAW12,  /* CyU3PMipicsiDataFormat_t dataFormat */

    4,                          /* uint8_t numDataLanes */

    2,                /* uint8_t pllPrd */

    89,            /* uint16_t pllFbd */

    CY_U3P_CSI_PLL_FRS_250_500M, /* CyU3PMipicsiPllClkFrs_t pllFrs */ 

    CY_U3P_CSI_PLL_CLK_DIV_4,    /* CyU3PMipicsiPllClkDiv_t csiRxClkDiv */

    CY_U3P_CSI_PLL_CLK_DIV_4,    /* CyU3PMipicsiPllClkDiv_t parClkDiv */

    0,                        /* uint16_t mClkCtl */

    CY_U3P_CSI_PLL_CLK_DIV_2,    /* CyU3PMipicsiPllClkDiv_t mClkRefDiv */

    1280,                /* uint16_t hResolution */

    50                            /* uint16_t fifoDelay */

};

3. Are there any more settings I need to add?

Best regards.