USB superspeed peripherals Forum Discussions

as soon as the fx3 receiving the data from parallel port , it make full signal.

and, the driver lib return the  "RES_TRANS_ERR".

Could you let me know why this is occurred ??

Firstly, I am using the "boot_fw" project in <SDK_ROOT>/firmware/boot_fw as the basis for my bootloader.

My goal is to have our device boot to this bootloader from SPI flash by default when it is turned on. It will then be recognized by the PC, and when our PC software runs, the PC software will quickly upload the latest version of the actual goal firmware that is shipped with our software to the FX3's RAM, and then have the bootloader boot the uploaded goal firmware.

Thus, I am using the USB_BOOT method inside of the "boot_fw" source code.

The only code I have changed are:

* The strings in the USB Device Descriptors (to rename the device).

* The VID and PID values (I have recompiled the host/Windows drivers to find these devices).

The "boot_fw" project was compiled and the image was uploaded to the device's SPI flash, from which it will boot at power up.

I can successfully upload the firmware to the CyFX3Device instance (which is correctly found and opened by the CyAPI library).

CyFX3Device::IsBootLoaderRunning() returns true before I call CyFX3Device::DownloadFw().

Furthermore, the internal method CyFX3Device::DownloadFwToRam() appears to return correctly. All of the downloaded FW data is uploaded back to the PC, and the byte-wise check/comparison shows that the data is correct.

However, as soon as the 0-length packet is sent to the device to tell it to call CyFx3BootJumpToProgramEntry(), Windows emits a "device disconnected" sound and the firmware doesn't seem to boot properly. None of the new device descriptors are sent to the PC, and no "device attached" sounds are emitted.

The device then reboots back to the bootloader firmware that was uploaded to the SPI flash.

The same Firmware image boots perfectly fine by uploading it to RAM using the built-in bootloader on the device.

So here is the general approach I have followed:

1. Use the "boot_fw" source code to compile a custom boot Fw image.

2. Upload this "boot_fw" image to SPI flash to be the default firmware that is booted.

3. Switch the FX3 out of bootloader/programming mode, so it loads the newly flashed "boot_fw" image by default.

4. Use CyAPI to download the intended device firmware to RAM, and have it boot.

Am I not doing something correctly? Should I be flashing my custom "boot_fw" to a different location, or is SPI flash okay?

I have an application which sets register values in an FPGA using the SPI out of the FX3.  Those register writes are initiated by the PC application over the USB interface to a control endpoint.  After writing the register (which starts a DMA in to the GPIF port) I initiate a bulk read over a different endpoint to get the image data.  If I don't insert a delay after the register write the bulk read to the image endpoint fails with WinUSB setting an error in the overlapped read request.  I have two questions:

     1) What happens to a USB request if a previous request is still being processed?  Is the callback delayed or does it execute but necessarily fail?

     2) Other than inserting a delay in the application after performing the register write how can I tell if the FX3 is ready to accept a USB command?

Thanks,

Greg

Hi

Is it possible to send pattern frame in UVC application from CX3 module FW in every DMA callback?

I try to modify dmaBuffer.buffer content, but the result seems only around 60 bytes data were modified that captured by USB wireshark.

What's wrong with my code or any limitation for change frame buffer?

          status = CyU3PDmaMultiChannelGetBuffer(chHandle, &dmaBuffer, CYU3P_WAIT_FOREVER);

       while (status == CY_U3P_SUCCESS)

        {

            /* Add Headers*/

            if(dmaBuffer.count < CX3_UVC_DATA_BUF_SIZE)

            {

#ifdef UVC_APPLICATION

                CyCx3UvcAppAddHeader ((dmaBuffer.buffer - CX3_UVC_PROD_HEADER), CX3_UVC_HEADER_EOF);

           CyU3PMemCopy(dmaBuffer.buffer+CX3_UVC_PROD_HEADER, ptrEEPROM, 0x4000);

#endif

Thanks

Angus

Hi,

I'm trying to use GPIO[8] on the FX3 as a GPIO for my application. After initializing the GPIO block, I call:

CyU3PDeviceGpioOverride(8, CyTrue);

CyU3PGpioSetSimpleConfig(8, &gpioConfig);

These API calls return CY_U3P_SUCCESS. However, whenever I read from GPIO[8], the input stage value is always zero, and setting the output does not change the pin output level. The exact same process works as expected for FX3 GPIO 7 and 9 (able to drive output and read input).

This behavior is present on the Cypress FX3 Superspeed explorer kit, as well as a custom FX3 based board (FX3 model CYUSB2014). Do you have any ideas why this might be happening? The complex block corresponding to GPIO[8] is in use by my application, but I'm attempting to configure the pin as a simple GPIO (GPIO[24] also works as expected).

Thanks,

Alex

Hi Sir,

i am trying to bringup a sensor, which having following spec.

1. 720Mbps data rate per lane, 2 lanes.

2. mipi lane count: 2 lanes

3. sensor resolution: 1280x480

4. fps:  120fps

5. RAW12.

the sensor's clocking cannot be adjustable, i keep it as what it is. trying to configure CX3 parameters.

1. clock divider

2. fifo delay

3. multipiler

4. pixclk

after trial and error for a week, i figured it out, that PIXCLK has to be more than 108MHz in order to get correct image streaming.

2 questions:

1. Is 108MHz PIXCLK ok?  as spec said the max GPIF clock is up to 100MHz.

2.  i attached my cx3 configuration for your comment seeking for better settings possible reducing pixclk rate to be below 100MHz..

I am working on a project which need transfer data from pc to FPGA. I used the slave FIFO.

the configure is:

16bits GPIF bus

DMA buffer size = 16K

DMA buffer COUNT = 4

DMA mode :  AUTO

if the PFGA runs at higher speed than the usb host OUT speed, the system runs very well. when the FPGA runs at a lower speed than the USB OUT speed, the transfer process can only run for several package and then blocked.

my guess:

It seems that if the FPGA runs at lower speed than USB OUT speed, the all 4 DMA  buffers have a risk to be all filled, once all the 4 DMA buffers are all filled, the AUTO OUT process terminate and can NOT recover.

is this correct?  if this is the case, how to make the process keep on going instead of termination when all 4 DMA buffers are filled ?

Hi,

During stress test, we found accidentally shows the error "DMA Reset Event: Commit buffer failure":

[2020-03-06 04:18:23] glFrameCount = 7784, glPacketCount=176 !

[2020-03-06 04:18:23] glFrameCount = 7785, glPacketCount=176 !

[2020-03-06 04:18:23] glFrameCount = 7786, glPacketCount=176 !

[2020-03-06 04:18:23] CyU3PDmaMultiChannelCommitBuffer Fail! status = 71 !

[2020-03-06 04:18:23] DMA Reset Event: Commit buffer failure

[2020-03-06 04:18:23] Application Stopped

[2020-03-06 04:18:23] Application Started

[2020-03-06 04:18:23] glFrameCount = 0, glPacketCount=198 !

[2020-03-06 04:18:23] glFrameCount = 1, glPacketCount=176 !

error status is CY_U3P_ERROR_INVALID_SEQUENCE.

when error occur, some image data will lose. It is not acceptable for us.

We use EZ-USB FX3 UVC cyusb3014, Please refer to the "AN75779 project. we do not do more modify.

I find many questions about "DMA Reset Event: Commit buffer failure" in forum, do you have any some solutions to resolve it?

Please kindly help me and thank you very much!

Jun

dear cypress experts

good day

regarding cx3 we are trying to use UVC and HID function,   we need HID function with set report and with interrupt out endpoint to get date from host.

please help to guide me how to implement this , i am refering CX3 HID example.

so far when try to add one interrupt out, window 10 will not recognize this device?

could you pls urgently help on this implementation?

br

jacky hu