Hello,

I see the following issue:

I am not able to install the driver for the FX3 Super Speed Explorer Kit.

I always see the following issue:

Cypress FX3 USB Bootloader Device

This security ID may not been assigned as the owner of this object.

(See screenshot below)

I have Windows 10 version 1709 installed.

J4 PMODE jumper is set in my setup.

In device manager the super speed explorer kit is visible as "West bridge" under other devices.

I first tried to install the driver from location: C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\driver\bin\Win10\x64

But it showed the error mentioned.

Because this did not worked I tried the installer from this thread with version 1.2.3.20:

Re: FX3 driver for windows10

But it shows the same error.

Can I please get help?

Thank you &

Best regards

Whether there are appropriate registers to configure the FX3 to work only in USB2.0 mode?  What is the power consumption of FX3 operating in USB2.0 and USB3.0 modes respectively

I am designing PCB using CYUSB3065-BZXC.

How much the maximum current consumption for VDD_MIPI of CX-3, if CX-3 is working MIPI 4 lane, 1Gbps/lane?

The datasheet doesn't say the working current consumption, but  suspended current.

Is there any information?

Best regards,

i'm working with CY7C65215 on linux and i'm trying to get it to work with 3M baud rate and flow control enabled.

i'm trying to read from the UART /dev/ttyACM0 to a file using the socat application.

sudo socat -u /dev/ttyACM0,b3000000,crtscts=1,echo=0,raw,ignoreeof CREATE:uart.bin

what I see that I get a lot of missing characters on the data (+lots of garbage).

i'm using Ubuntu 18.04.4 LTS with 5.3.0-42-generic kernel

on windows with the lastest driver there is no issue - all data arrives without any garbage.

on linux it uses the default cdc_acm driver - and i suspect there might be an issue with either the high baud rate or with flow control.

is there any way to debug this ?

I am using CX3 RDK Dev A board,

If I build the code this error occurred  section `.data' will not fit in region `DATA', region `DATA' overflowed by 12960 bytes

so i try to modify fx3.ld file as below:

MEMORY

{

I-TCM : ORIGIN = 0x100 LENGTH = 0x3F00

SYS_MEM : ORIGIN = 0x40003000 LENGTH = 0x2D000

DATA : ORIGIN = 0x40030000 LENGTH = 0xD000

}

i also modify #define CY_U3P_MEM_HEAP_BASE         (0x40038000)  to #define CY_U3P_MEM_HEAP_BASE         (0x4003D000)

and build successfully.

but after modification,  i found an new error as below:

AppInit:DmaMultiChannelCreate Err = 0x10

AppInit:MultiChannelReset Err = 0x40

So what I should do to solve the error?

Hi everyone,

I'm developing an application based on the MSC example for the FX3S. In some cases, I need to manually read/write data to the storage.

This is the DMA configuration:

CyU3PDmaChannelConfig_t dmaConfig;
dmaConfig.size = 512;
dmaConfig.count = CY_FX_MSC_DMA_BUF_COUNT;
dmaConfig.prodSckId = (CyU3PDmaSocketId_t) (CY_U3P_UIB_SOCKET_PROD_0 | CY_FX_MSC_EP_BULK_OUT_SOCKET);
dmaConfig.consSckId = CY_U3P_SIB_SOCKET_0;
dmaConfig.dmaMode = CY_U3P_DMA_MODE_BYTE;
dmaConfig.notification = CY_U3P_DMA_CB_RECV_CPLT | CY_U3P_DMA_CB_SEND_CPLT | CY_U3P_DMA_CB_PROD_EVENT | CY_U3P_DMA_CB_CONS_EVENT;
dmaConfig.cb = UsbStorage_DmaStorageWriteCb;
dmaConfig.prodHeader = 0;
dmaConfig.prodFooter = 0;
dmaConfig.consHeader = 0;
dmaConfig.prodAvailCount = 0;
status = CyU3PDmaChannelCreate(&glChHandleMscOut, CY_U3P_DMA_TYPE_MANUAL, &dmaConfig);
dmaConfig.prodSckId = CY_U3P_SIB_SOCKET_1;
dmaConfig.consSckId = (CyU3PDmaSocketId_t) (CY_U3P_UIB_SOCKET_CONS_0 | CY_FX_MSC_EP_BULK_IN_SOCKET);
dmaConfig.notification = CY_U3P_DMA_CB_RECV_CPLT | CY_U3P_DMA_CB_SEND_CPLT | CY_U3P_DMA_CB_PROD_EVENT | CY_U3P_DMA_CB_CONS_EVENT;
dmaConfig.cb = UsbStorage_DmaStorageReadCb;
status = CyU3PDmaChannelCreate(&glChHandleMscIn, CY_U3P_DMA_TYPE_MANUAL, &dmaConfig);

I am using the following command sequence to initiate a read/write request. (Each return status check here is omitted for brevity: every call returns SUCCESS until WaitForCompletion).

// Prepare the DMA Buffer
CyU3PDmaBuffer_t dmaBuf;
dmaBuf.buffer = buf;
dmaBuf.status = 0;
dmaBuf.size = (len + 15) & 0xFFF0; // Round up to a multiple of 16.
dmaBuf.count = len;
CyU3PDmaChannel *handle = (isRead) ? &glChHandleMscIn : &glChHandleMscOut;
if(isRead)
    CyU3PDmaChannelSetupRecvBuffer(handle, &dmaBuf);
else
    CyU3PDmaChannelSetupSendBuffer(handle, &dmaBuf);
CyU3PSibReadWriteRequest(isRead, ((lun >= CY_FX_SIB_PARTITIONS) ? 1 : 0), glLunUnit[lun], len / CY_FX_SIB_MAX_BLOCK_SIZE, startAddr, 1);
ret = CyU3PDmaChannelWaitForCompletion(handle, CYU3P_WAIT_FOREVER); // ret == "ABORTED" when trying to write!

Reads are successful. When trying to WRITE, the DmaStorageWriteCb callback is not called and the WaitForCompletion function returns ABORTED.

I've checked the docs and the forums and couldn't find an answer. Can you help me?

Thanks,
Salvatore

Hi, I knew the manual DMA mode could get a callback from PC, if PC has already received data from DMA buffer by FinishDataXfer().

However, I use AUTO DMA mode now. I need to do something on FX3 after PC has received desired data size.

Now, my way is PC send a no-data request by control endpoint after that.

Curiously, is there any function or mechanism from FX3 API to get the information on AUTO DMA mode?

Best Regards,

Hughes

1. Import AN87216 Master/Slave projects and built them.

2. Let GPIF designer directly output to the cyfxgpif_syncsf.h in the projects and overwrite them

3. Go back to Eclipse and it will even tell you the files are updated and need fresh. Build Master/Slave projects, no action.

4. Modify cyfxgpif_syncsf.h manally and save and build, both project will be rebuilded.

Sometimes a build in GPIF designed does trigger rebuild in Eclipse.

Hi Cypress

Do you have FX3 GPIO status table in Reset period for reference , Thank !!

Dear...

I have seen in the CX3 Datasheet, page 10 (Figure 4) the Power-up sequence drawing. Unless there is an error in the specification, it clearly shows that VDDIO1 should go up before 10ms after VBUS and VDD, it means that VDDIO1 could be raised up with the rest of voltage rails (VBUS and VDD) at the same time.

I need to be sure about it because in the CX3 reference schematic from e-ConSystems (DENEBOLA), the voltage regulator supplying power to VDDIO has a Soft Start configuration with more than 180ms.! which violates the power-up sequence.

I would appreciate your comments.