USB superspeed peripherals Forum Discussions

Hello,

I am trying to stream data from a 1008x800 raw10 ensor to standard UVC application (Amcap, VLC).

I can successfully stream if I use 16bit bus and I select CY_U3P_CSI_DF_YUV422_8_2 format in CyU3PMipicsiSetIntfParams, but I would like to make it work also using 24bit GPIF bus.

To set 24bit bus I changed the definition of GPIF_BUS_WIDTH from CY_U3P_MIPICSI_BUS_16 to CY_U3P_MIPICSI_BUS_24, but the streaming doesn't work, I don't understand why. I probed HSYNC and VSYNC and they are toggling with the correct timing.

The line size is a multiple of 24 bits and the buffer size is 36kB, so it's a multiple of 24 bits.

Here are my settings for 24bit case:

CyU3PMipicsiCfg_t OH02A10_RAW10_1008x800 = 

{

    CY_U3P_CSI_DF_YUV422_8_2,  /* CyU3PMipicsiDataFormat_t dataFormat */

    2,                          /* uint8_t numDataLanes */

    2,                /* uint8_t pllPrd */

    89,            /* uint16_t pllFbd */

    CY_U3P_CSI_PLL_FRS_250_500M, /* CyU3PMipicsiPllClkFrs_t pllFrs */ 

    CY_U3P_CSI_PLL_CLK_DIV_4,    /* CyU3PMipicsiPllClkDiv_t csiRxClkDiv */

    CY_U3P_CSI_PLL_CLK_DIV_4,    /* CyU3PMipicsiPllClkDiv_t parClkDiv */

    0,                        /* uint16_t mClkCtl */

    CY_U3P_CSI_PLL_CLK_DIV_2,    /* CyU3PMipicsiPllClkDiv_t mClkRefDiv */

    1008,                /* uint16_t hResolution */

    50                            /* uint16_t fifoDelay */

};

and here is the SS descriptor:

/* GUID, globally unique identifier used to identify streaming-encoding format */

//rgb565

0X7B,0XEB,0X36,0XE4,

0X4F,0X52,0XCE,0X11,

0X9F,0X53,0X00,0X20,

0XAF,0X0B,0XA7,0X70,

0x10,  //Number of bits per pixel: 16

0x01, //Optimum Frame Index for this stream: 1 (1008x800)

0x00,  //X dimension of the picture aspect ratio; Non-interlaced

0x00,  //Y dimension of the pictuer aspect ratio: Non-interlaced

0x00,  //Interlace Flags: Progressive scanning, no interlace

0x00,  //duplication of the video stream restriction: 0 - no restriction

/* Class specific Uncompressed VS Frame Descriptor 1 - 1008x800 */

    0x1E,                                //Descriptor size

    CX3_CS_INTRFC_DESCR,                 //Descriptor type

    0x05,                                //Subtype:  frame interface

    0x01,                               // Frame Descriptor Index: 1

    0x00,                                //No Still image capture method supported

    0x76,0x02,                         // Width in pixel:  1008*10/16=630(0x276)

    0x20,0x03,                          //Height in pixel: 800

    0x00,0xc0,0x9b,0x1c,              //Min bit rate (bits/s): 630 x 800 x 16 x 59.52= 479969280(0x 1C9BC000)

    0x00,0xc0,0x9b,0x1c,              //Max bit rate (bits/s): Fixed rate so same as Min

    0x80,0x61,0x0f,0x00,              //Maximum video or still frame size in bytes(Deprecated): 630 x 800 x 2=1008000(0xF6180)

    0x4a,0x90,0x02,0x00,              //Default frame interval (in 100ns units): (1/59.52)x10^7

    0x01,                                //Frame interval type : No of discrete intervals

    0x4a,0x90,0x02,0x00,             // Frame interval 3: Same as Default frame interval

here is the probe control settings:

/*UVC Probe Control Settings */

uint8_t glProbeCtrl[CX3_UVC_MAX_PROBE_SETTING] = {

    0x00, 0x00,                         // bmHint : No fixed parameters

    0x01,                                //Use 1st Video format index

    0x01,                               // Use 1st Video frame index

    0x4a,0x90,0x02,0x00,             // Desired frame interval in 100ns = (1/30)x10^7

    0x00, 0x00,                          //Key frame rate in key frame/video frame units

    0x00, 0x00,                          //PFrame rate in PFrame / key frame units

    0x00, 0x00,                          //Compression quality control

    0x00, 0x00,                          //Window size for average bit rate

    0x00, 0x00,                          //Internal video streaming i/f latency in ms

    0x80,0x61,0x0f,0x00,              //Maximum video or still frame size in bytes(Deprecated): 630 x 800 x 2=1008000(0xF6180)

#ifdef CX3_UVC_1_0_SUPPORT

    0x00, 0x90, 0x00, 0x00              // No. of bytes device can rx in single payload: 32KB

#else

    /* UVC 1.1 Probe Control has additional fields from UVC 1.0 */

    0x00, 0x90, 0x00, 0x00,              //No. of bytes device can rx in single payload: 32KB

    0x00, 0x60, 0xE3, 0x16,              //Device Clock

    0x00,                                //Framing Information - Ignored for uncompressed format

    0x00,                                //Preferred payload format version

    0x00,                                //Minimum payload format version

    0x00                                 //Maximum payload format version

#endif

};

/* UVC Probe Control Setting - 1008x800 */

uint8_t const gl1008x800ProbeCtrl[CX3_UVC_MAX_PROBE_SETTING] = {

    0x00, 0x00,                         // bmHint : No fixed parameters

    0x01,                               // Use 1st Video format index

    0x01,                               // Use 1st Video frame index

    0x4a,0x90,0x02,0x00,             // Desired frame interval in 100ns = (1/30)x10^7

    0x00, 0x00,                         // Key frame rate in key frame/video frame units

    0x00, 0x00,                         // PFrame rate in PFrame / key frame units

    0x00, 0x00,                         // Compression quality control

    0x00, 0x00,                         // Window size for average bit rate

    0x00, 0x00,                         // Internal video streaming i/f latency in ms

    0x80,0x61,0x0f,0x00,             // Maximum video or still frame size in bytes(Deprecated): 630 x 800 x 2=1008000(0xF6180)

#ifdef CX3_UVC_1_0_SUPPORT

    0x00, 0x90, 0x00, 0x00              // No. of bytes device can rx in single payload: 36KB

#else

    /* UVC 1.1 Probe Control has additional fields from UVC 1.0*/

    0x00, 0x90, 0x00, 0x00,             // No. of bytes device can rx in single payload: 36KB

    0x00, 0x60, 0xE3, 0x16,             // Device Clock

    0x00,                               // Framing Information - Ignored for uncompressed format

    0x00,                               // Preferred payload format version

    0x00,                               // Minimum payload format version

    0x00                                // Maximum payload format version

#endif

};

Can you help me understand what is the issue?

Thanks,

Riccardo

Hello,

I'm using the FX3 library in windows and linux system.

At Windows enviroment, i send a command to FX3 Fw using "CCyControlEndPoint->XferData" function. (refer below code)

CCyControlEndPoint* ept = USBDevices.ControlEndPt;

ept->Target = TGT_DEVICE; //(0x00)

ept->ReqCode = 0xBC; // pre-defined in FX3 firmware.

ept->ReqType = REQ_VENDOR; //(0x40)

ept->Direction = DIR_TO_DEVICE; //(0x00)

ept->Value = 0x00;

ept->Index = 0x00;

unsigned char  buf[1] = { 0x00};

bool bXferCompleted = ept->XferData(buf, length);

At Linux environment, i send a same command using "cyusb_control_transfer" function.

mHandle = cyusb_gethandle(mDeviceDB->cyDevId);

unsigned char  buf[1] = { 0x00 };

cyusb_control_transfer(mHandle, 0x40, 0xBC, 0x00, 0x00, buf, 1, 1000);

However, It works only Windows environment. Even with the USB monitoring tool, the command seems to be sent well.

Am I using the function incorrectly in the Linux environment?

How do I implement it in Linux to send commands the same as in Windows?

I am testing with a couple examples from the FX3 SDK (namely the usb HID Mouse example). I modified the code slightly so that it will continuously send mouse circles, but if I put the computer to sleep, or if I restart the computer the circles stop, and I have to press the gpio button again to re initiate the circles.

My question is what events need to be handled in order to properly handle a sleep or a restart on the host?

Hi I have a simple application on the FX3 which just turns an LED on, I then shut off my computer and the LED remains on. What should I do if I want the LED to shut off when the computer is off?

Hello,

I am using the slave fifo implementation provided with no code changes in what respects the slave fifo.

(only added very little code to implement a few vendor commands to control GPIO lines).

The full application works perfect but sometimes FX3 starts with flag_a low and as a consequence nothing will work afterwards.

The PC aplic at startup reads data to flush all buffers but there no data is available at bulk ep. (actually no data was written to the

slave fifo so there is no reason for the flagA to be low).

This is a somehow rare situation but even so if I reset the FX3 many times I can see this happening a few times.

When this happens the Flag_a actually gets high for about 5us and then goes low and stays there forever.

I am sure that nothing is written to the slave-fifo, as the WE is high all the time, while PCLK has a running clock.

I really wish is to have a way to really reset/initialize the slave fifo to a know initial state.

(on my application I do have a vendor cmd that does a initialization of the FPGA I have connected to the FX3

I would like to add the necessary code lines to be sure I got the slave fifo fully reset too so that I init FPGA and slave-fifo

and stay assured that all is ready to go ).

Is there a programatic way to reset/initialize the slave fifo interface to be sure it gets in the proper state ?

Or is this flag_a low issue a know issue that I can solve somehow ?

Thanks.

Luis C.

Hi,

I having problems specifying and sourcing a 52 Mhz CMOS oscillator at 3.3V for the CYUSB3014.  Is there a recommended PN?  And is there a reference schematic design and layout?

Don't need the extra processing speed now, just trying to future-proof.

Thanks,

Greg

Electronics Test Engineer

Hi there,

I'm fighting with data lost during DMA transfer and totally stuck on two questions... To be sure that received data is monotonic I attached an FPGA which works as a basic counter. FPGA sends to FX3 512 byte blocks, each block filled by 16-bit block number. For example, first 512 bytes of data filled by 0x0000, 2nd 512 bytes filled by 0x0001, 3rd 512 bytes filled by 0x0002 and so on. Verilog source code is below.

module main(
    input RD,
    input RST,
    output [15:0] DATA,
output LED
    );
reg [23:0] counter;
always @(negedge RST or posedge RD)
begin
if (!RST)
counter <= 0;
else
counter <= counter + 24'd1;
end
assign DATA = counter[23:8];
assign LED = counter[13];
endmodule

FX3 GPIF configured as master async device, each DATA_IN action asserts RD output.

DMA configuration:

    dmaCfg.size = 16384;
    dmaCfg.count = 1;
    dmaCfg.prodSckId = CY_U3P_PIB_SOCKET_0;
    dmaCfg.consSckId = CY_U3P_UIB_SOCKET_CONS_1;
    dmaCfg.dmaMode = CY_U3P_DMA_MODE_BYTE;
    dmaCfg.notification = 0;
    dmaCfg.cb = NULL;
    dmaCfg.prodHeader = 0;
    dmaCfg.prodFooter = 0;
    dmaCfg.consHeader = 0;
    dmaCfg.prodAvailCount = 0;

As soon as vendor code received data transfer starts with CyU3PGpifSMSwitch() API. Every tyme I'm trying to get exactly 16384 bytes of data through bulk IN EP, no less, no more, because GPIF SM uses LD_DATA_COUNT action and grabs only 8192 words (16384 bytes). But unfortunately sometimes I see a data lost in the MIDDLE of transfer. Sometimes data received correctly, sometimes not. And as I see when data lost happens, it's always happens at the same offset between 0x0008 and 0x0009 words as on the 3rd picture below.

So my first question is what I missed? Should I change something in GPIF or DMA config?

Hello,

Sometimes after a manual hard reset (without powering off everything) the boot defaults to USB and the code stored in the eeprom is no longer read.

I did my research an found that for some unknown reason SDA gets low and then the FX3 assumes the i2c bus is in use and default to USB boot.

After that no matter what I do it will stay like this forever and I need to take power off and turn it all back on.

When powering it up all works perfect all the times. It is only if I apply a manual hardware reset with the chip powered that sometimes it locks up in this state.

Is there a way to avoid this situation ?

Thanks.

Luis C.

Hello, I asked this question two years ago ,

Re: When usb3.1 Gen 2 FX3 chip will be released?

Now is 2020 , I am still waiting for GEN2 Controller....and the newest roadmap shows that FX3GEN2 is still unavailable.

If its possible, could you please give a cue about the detail developing info of FX3GEN2  please?

Thank you.