USB superspeed peripherals Forum Discussions
I am considering replacing the Renesas USB Host Controller with FX3.
R8A66597FP is mounted on the current board.
Code Example has an example of USB Host (cyfxusbhost).
Is it possible for this CE to replace the current device?
Thanks,
Tetsuo
Show LessHi,
In cyfxusbi2cregmode, glEp0Buffer doesn't need to be 32 bytes aligned because it is only used in setup messages, and CyU3PUsbGetEP0Data and CyU3PUsbSendEP0Data don't use DMA to transfer the data.
Is this correct?
Thanks
Lucas
Show LessCYUSB3KIT-003+AN75779 not working
anybody could help me?
I configure 2 board with ov7725, to get easy analysis, I use a very slow rate: 640*480*30FPS, YUV2.
I'm sure that both I2C image sensor configuration are OK! the image sensor is giving the right signal.
(1) my customer board cyusb3014+FPGA+imagesensor, I use FPGA as an intermediate device to capture signals to my PC for analysis , FPGA get imagesensor signals and then forward to cyusb3014, the job is extremely simple, all meaning ful FPGA code is given as follows,
reg LV_reg=0,FV_reg=0,PCLK_reg=0;
reg [15:0]DQ_reg;
always@(posedge cmos_pclk)begin
LV_reg <= cmos_href;
FV_reg <= cmos_vsync;
DQ_reg <= {8'd0,cmos_data};
end
always@(posedge cmos_pclk)begin
LV <= LV_reg;
FV <= FV_reg;
DQ <= DQ_reg;
end
assign PCLK = cmos_pclk;
where LV, FV, DQ, PCLK are output wires to cyusb3014 directly
The custom board works fine!
(2) the same code was used for CYUSB3KIT-003, but I cannot get a trace of image. (FAILED anyway)
the configuration is similar to
I cannot figure out what is the problem....
Show LessHi,
We use EZ-USB FX3, Source code is base the "AN65974" project.
We want to change bulk mode to isochronous, but failed. Could you help us to set it?
Thank you very much!
Attachment is the source code.
Show LessHello,
As I managed to get streaming working on Denebola kits we went further into developing our solution (there is coax ser-des between sensor and CX3). Two of the boards are working as expected (we still have issues with SerDes but they were expected and will be fixed in near future). Because we had to strenghen our numbers we ordered three more boards - and no MIPI lock condition on receiver is seen despite using same firmware and same custom extension board. Have anyone experienced similar behavior?
Hello everyone!
I have a problem with the DmaMultiChannel used for the frame transmission on the CX3 when working on a custom uvc host app.
I'll explain you the problem in the following steps:
- If I use a UVC host app such as e-CAMView I don't have problems when, after flashing the FW in the CX3 I start and restart the Frame transmission (by opening and reopening e-camview).
- With the Custom Uvc Host app that I previously mentioned, when I first start the streaming after rebooting the FW I have a normal transmission. When I send the command to stop the transmission I somehow generate an overflow on the DMA multichannel: I can easily notice this by using, as soon as the function CyCx3UvcAppStop is activated, a CyU3PDmaMultiChannelGetBuffer command. At this point I noticed (thanks to the UART debugger) that the status of the DmaMultiChannel buffer is set to 0x8 (CY_U3P_DMA_BUFFER_OCCUPIED) and that the channel count parameter is equal to the size of the buffer. From a comparison with the output of e-camview, I know that at this point of the execution the status should be set to 0x0 and the count to 0x0.
- Even if in the UvcAppStop function I perform the standard reset of the channel and the EP cleanup, when I restart the uvc host app the DmaMultiChannel is still on the same status (CY_U3P_DMA_BUFFER_OCCUPIED) and I get the CyU3PDmaMultiChannelCommitBuffer error 0x47 (CY_U3P_ERROR_INVALID_SEQUENCE) when the UVC thread starts running. More specifically, the reset that I perform is the following:
CyU3PMipicsiSleep(),
CyU3PGpifDisable(CyFalse);
glIsApplnActive = CyFalse;
CyU3PUsbSetEpNak(CX3_EP_BULK_VIDEO, CyTrue);
CyU3PBusyWait(100);
CyU3PDmaMultiChannelReset(&glChHandleUVCStream);
CyU3PThreadSleep(25);
CyU3PUsbFlushEp(CX3_EP_BULK_VIDEO);
CyU3PUsbSetEpNak(CX3_EP_BULK_VIDEO, CyFalse);
CyU3PBusyWait(200);
if (glIsClearFeature) {
CyU3PUsbStall(CX3_EP_BULK_VIDEO, CyFalse, CyTrue);
glIsClearFeature = CyFalse;
} - The only effective solution to restart the DmaMultiChannel so far is to unplug and replug the device and to flash the FW again.
I think that the problem might be related to the UvcHostApp not consuming the buffer committed the the consumer socket when I stop the execution, thus generating some sort of overflow. I tried to apply this suggestions without success Invalid Sequence Error in Multi-Channel Commit Buffer - KBA218830 .
Do you have any suggestions on where the problem could be? Do you know why the DMaMultiChannnel is not properly reset?
I thank you in advance for your answer.
Best regards,
Costantino
Show LessWe are implementing 2nd bootloader, which has EEPROM writing/update capability and will reside in I2C-access EEPROM, for FX3, CYUSB3013-BZXC. There is an urgency and preference to finish within a few days.
Background,
- We use the following Cypress FX3 example project for bootloader and EEPROM writing.
- Cypress FX3 SDK1.3.4
- 1. (for 2nd bootloader) EZ-USB FX3 SDK\1.3\firmware\boot_fw
- 2. (for EEPROM writing/update) EZ-USB FX3 SDK\1.3\firmware\basic_examples\cyfxflashprog
- FX3 Fail Safe Firmware Update
- Cypress FX3 SDK1.3.4
- Current status on Cypress FX3 explorer kit
- 2nd bootloader was implemented by using above 1.1 sample project. We have some stable issue but can tolerate for now.
- EEPROM writing/update by 2nd bootloader is briefly tried out by using above 1.2 sample project. It hangs.
Here are questions.
- (most important task) Writing EEPROM from 2nd bootloader
- We saw DMA setup is configured along with EEPROM writing in above 1.2 sample project. Initial tryout of this project hangs. Is there a simple sample project of EEPROM writing or reading sample project without DMA we can use to simplify things?
- Is there any Cypress sample project other than above 1.2 sample project we can or should use?
- Debugging tools
- UART output is not working from 2nd bootloader but working from multi-thread functions. Any comment?
- 2nd Bootloader - Cypress bootloader doesn’t load successfully 2nd bootloader every time from EEPROM to RAM.
I am developing an application on Windows 10. This application accesses a FPGA board through USB. I am using CyAPI.lib library. However I am not able to get Windows 10 drivers for USB.
Hardware details are as follows.
Device Name: FX3_USB3_1.0.0
Hardware Id: USB\VID_04B4&PID_1212&REV_0000
I searched online regarding this and found this link http://www.cypress.com/knowledge-base-article/drivers-ez-usb-fx1-fx2lp-and-fx3-kba94413 . I followed the steps mentioned in the document and added vendor, product ids to .inf file. I think simply adding ids to .inf file doesn't solve the problem because after making these changes an error message regarding .cat file popped up.
On further searching I came across this link https://www.cypress.com/documentation/software-and-drivers/ez-usb-fx3-software-development-kit . In this page "EZ-USB FX3 SDK 1.3.4 for Windows" link leads to nowhere. So, I downloaded the source code and tried to build the driver with Visual Studio 2019 (this is the only version of Visual Studio I have), When I built the project following two errors came (1)error 1209: Section [sourcedisksfiles] is defined multiple times. (2)error 1209: Section [destinationdirs] is defined multiple times. I am new to driver development so I don't have any idea what these errors mean and how to resolve them.
Kindly guide me as to how to get Windows 10 drivers.
Show LessOur setup gets data from the fast ADC which is connected to FPGA. FPGA through CYUSB3014 working in SuperSpeed mode and
send data to the PC. We use slightly modernized SlaveFifo synchronous firmware from AN65974 (cyfxslfifosync.c and cyfxslfifosync.h have been attached).
Usually data transmitted fine but sometimes USB controller freezes - FPGA has data to sent but libusb_bulk_transfer() reads
0 bytes with timeout error (timeout variable in libusb_bulk_transfer sets to 200 ms). The freeze could be overcome with the help of libusb_reset_device() function
from PC. After that, libusb_bulk_transfer() works fine until next freeze.
From the primary analysis it seems that the freeze is due to the fact that the callback function of the producer event (CyFxSlFifoPtoUDmaCallback) is not called.
Probably the freeze happens when the PC tries to read data when the endpoint buffer in the CYUSB3014 is partially filled.
In a case when initially no data on FPGA (FIFO buffer is empty) all works fine and no freeze are observed after data becomes available.
PC OS: x86_64 Ubuntu Linux 18.04.4 LTS
libusb 1.0.21-2
CYUSB3014 connected to USB 3.0 port on PC.
Is it possible to prevent the freezes without libusb_reset_device() call?
Show LessHi,
"FX3Device-> IsBootLoaderRunning ()" returns quickly when it is a boot loader, but it takes a lot of time otherwise.
I want to know how to make it faster.
Regards,
Takao
Show Less