USB superspeed peripherals Forum Discussions

Hi All! 

I'm trying to figure it out how make my own application by "Slave FIFO Interface" Example.

I use AN65974 document: "Designing with the EZ-USB FX3 Slave FIFO Interface".

I have "cyfxgpif2config.h" header generated by GPIFII Designer.

The AN65974 document  says  next: "This header file must be included in the firmware project" (Part 10 on page 23).

Also AN65974 says "The EZ-USB FX3 SDK includes a firmware example that integrates the Slave FIFO
interface".

I was trying to figure out how I can integrate this header into the firmware project by studying "SYNCHRONOUS SLAVE FIFO PROTOCOL EXAMPLE", but I couldn't figure out how to do it.

Help me please understend how I can integrate "cyfxgpif2config.h" header into the firmware project.

Hi Sir,

I saw a question about continue clock in the below path

https://community.cypress.com/t5/USB-Superspeed-Peripherals/Cypress-CX3-solution-Clock-Continuous-mode/m-p/54215

Q1: if my Serdes is non-continue clock, Can I use the same initial flow in non-continue clock ?  

Q2: if the answer of Q1 is No, just keep the initial flow from code Gen(Image Sensor Configuration )? Or Any other suggest?

Best Regards,

BenWang

At CX3, 

Sometimes (frequently) "CB Failure" is happened. 

After "CB Failure" was happend,  "ApInstop -> ApInStart"

(Now, system is working on 97fps, 1920x1200)

Logs (UART) are belows

==================================================

AplnStrt:SMState = 0x1
CB failure
AplnStop:SMState = 0x9
AppStart

AplnStrt:SMState = 0x2
CB failure
AplnStop:SMState = 0x7
AppStart

AplnStrt:SMState = 0x1
CB failure
AplnStop:SMState = 0x9
AppStart

AplnStrt:SMState = 0x2
CB failure
AplnStop:SMState = 0x5
AppStart

================================================

 Please, let me know how to fix it.

(I think when it was happened, system performance maybe is too low.) 

Hi, I knew the DR_GPIO action corresponds to Output Signal Setting. I’ve studied GPIFII_Designer_User_Guide, and have 2 questions for the GPIO polarity.

Q1:

What is “new value”? (or I can ignore the word)

Q2: According to the description for Output Signal Settings - Polarity:

Besides, DR_GPIO action CANNOT select the polarity in Assert mode.

Therefore, if Output Signal Settings - Polarity sets Active High, when DR_GPIO action is executed, the pin’s polarity will ALWAYS be high?

Any help will be highly appreciated!

Hi, I knew that the GPIF2: IN_DATA - Register corresponds to CyU3PGpifReadDataWords().

I’m more familiar with GPIF2: IN_DATA - Socket which links to DMA channel to receive data. After the data is full, it triggers callback function in FW.

It seems that the GPIF2: IN_DATA - Register don’t use the callback mechanism. Developer should call CyU3PGpifReadDataWords() in the FW manually.

Besides, I’ve studied the GPIF_EXAMPLE1.zip in third reply.

According to the GPIF_EXAMPLE1.zip - Slave Device, it seems that the FW calls CyU3PGpifReadDataWords() every second, which is ASYNC with state machine’s IN_DATA - Register.

Q1: If CyU3PGpifReadDataWords() is called earlier than GPIF2: IN_DATA – Register, CyU3PGpifReadDataWords() will return CY_U3P_ERROR_FAILURE or else?

Q2: If GPIF2: IN_DATA – Register is executed earlier than CyU3PGpifReadDataWords(), GPIF2: IN_DATA – Register  state will wait CyU3PGpifReadDataWords() before GPIF goes to next state?

Q3: what’s the different between the GPIF2: IN_DATA – Register and GPIF2: IN_DATA – Socket? Is the former slow?

Any help will be highly appreciated!

Hello,

During debugging a new camera design using the CX3, I began getting Abort Handler interrupts (in cyfxtx.c).  I have never seen these before and there's virtually no information about them in the CX3 or FX3 technical reference manual.

Can anyone explain what causes them?

Thanks,

Scott

Hello

I'm referring to the FX3 datasheet reset sequence Figure 29
Please tell me if the following understanding is correct
#1. Is it correct to understand that the power supply stabilization time before releasing the H/W reset is tRPW = 1ms (Min)?
#2. Is it correct to understand that the clock stabilization time before releasing the H/W reset is tRPW = 1ms (Min)?

#3. Assuming SPI boot, the sequence after H/W reset release is recognized as follows.
Correct?
 After H / W reset release → PLL lock start → PLL lock complete → IC internal reset release → SPI access start (boot image load start)
Please let us know, if tere are some misunderstanding mentioned above.

Best Regards

Arai

Hi all

Here`s a strange problem, XferData() may failed when slave endpoint sent a short packet with a particular length.

we`re trying to transfer data from FPGA to PC host by FX3, FX3 runs with a slave FIFO firmware, EP2 IN(0x82) is initiated in FX3 for BULK IN transferring, in each transfer test, firstly, PC host invoke XferData() to generate a BULKIN transfer(bufLen is always set 16384, pktMode is set TRUE) and waiting for a packet from FX3, then our FPGA send a short packet to FX3, at each test,packet length is different, short packet is ended by asserted the PKT_END pin .

XferData() return TRUE in most of tests, but failed at  several test, after research of these failed tests, we found that if FPGA send packet with length of 2048,4096 or 8192, XferData() retrun FALSE and timed out happened, such a werid thing. any body can help me ?

BTW,  these two results may help you:

1.XferData() can be successful when actual length is 8191 or 8193, but if FPGA send 8192 bytes to FX3, XferData() must be failed.

2.if we set 8192 to bufLen parameter, XferData() return TRUE when FPGA send 8192 bytes to FX3.

here`s main part of BULKIN transfer code at PC host side(VS2013):