USB superspeed peripherals Forum Discussions
Hello,
During debugging a new camera design using the CX3, I began getting Abort Handler interrupts (in cyfxtx.c). I have never seen these before and there's virtually no information about them in the CX3 or FX3 technical reference manual.
Can anyone explain what causes them?
Thanks,
Scott
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Hello
I'm referring to the FX3 datasheet reset sequence Figure 29
Please tell me if the following understanding is correct
#1. Is it correct to understand that the power supply stabilization time before releasing the H/W reset is tRPW = 1ms (Min)?
#2. Is it correct to understand that the clock stabilization time before releasing the H/W reset is tRPW = 1ms (Min)?
#3. Assuming SPI boot, the sequence after H/W reset release is recognized as follows.
Correct?
After H / W reset release → PLL lock start → PLL lock complete → IC internal reset release → SPI access start (boot image load start)
Please let us know, if tere are some misunderstanding mentioned above.
Best Regards
Arai
Show LessHi all
Here`s a strange problem, XferData() may failed when slave endpoint sent a short packet with a particular length.
we`re trying to transfer data from FPGA to PC host by FX3, FX3 runs with a slave FIFO firmware, EP2 IN(0x82) is initiated in FX3 for BULK IN transferring, in each transfer test, firstly, PC host invoke XferData() to generate a BULKIN transfer(bufLen is always set 16384, pktMode is set TRUE) and waiting for a packet from FX3, then our FPGA send a short packet to FX3, at each test,packet length is different, short packet is ended by asserted the PKT_END pin .
XferData() return TRUE in most of tests, but failed at several test, after research of these failed tests, we found that if FPGA send packet with length of 2048,4096 or 8192, XferData() retrun FALSE and timed out happened, such a werid thing. any body can help me ?
BTW, these two results may help you:
1.XferData() can be successful when actual length is 8191 or 8193, but if FPGA send 8192 bytes to FX3, XferData() must be failed.
2.if we set 8192 to bufLen parameter, XferData() return TRUE when FPGA send 8192 bytes to FX3.
here`s main part of BULKIN transfer code at PC host side(VS2013):
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I am not sure how to configure the MIPI receiver for the CX3
We are using AR1335 image sensor and I have attached parameters which we have given in tool, we are trying to generate test pattern but nothing is streaming
kindly give your feedback
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Hello,
I have more than 4 actions in some states (to drive multiple CTRL outputs), but somehow the designer GUI only allows me to see the first 4 actions in each state. Is there a way to re-size the state block on the GUI, so that I can see and select/config all the actions in those states?
Thanks,
Henry
Show LessHello
I got the sample FW of FX3 + CYUSB3ACC-007 from the link below.
https://japan.cypress.com/documentation/other-resources/superspeed-device-design-example-john-hyde
However, I don't know what video format is supported.Could you please tell me on this?
In addition, The customer wants to transfer YUV2 video data with FX3 + CYUSB3ACC-007, and Video transfer from CPLD .
Is their sample project mentioned above.
Best Regards
Arai
Hi, our FPGA will send two different format data:
- Img Data: It needs to send out to PC.
- Info Data: FX3 parses this data and don’t need to send out.
There is one pin “Switch_pin” which provided by FPGA to decide the data format is Img Data or info data.
Therefore, in the GPIF, I want to use “Switch_pin” to judge how to handle this data in FX3. Pseudo code:
If the data is Img Data, FX3 uses CY_U3P_DMA_TYPE_AUTO_MANY_TO_ONE to receive it, and then send out to PC by USB bulk endpoint directly.
If the data is Info Data, FX3 uses CY_U3P_DMA_TYPE_MANUAL_MANY_TO_ONE to receive it, and parse it inside the FX3 CPU.
It means that GPIF can decide that it want to use Auto DMA or Manual DMA to receive one piece of data, and the data will be handled differently in FX3.
Is it possible to achieve?
Any help will be highly appreciated!
Show LessQuestions:
1. The FX3 SSE implements on board JTAG and UART interfaces with a USB bridge chip. This additional logic is undesirable in our application. Use of a JLink device is recommend by Cypress. Which JLink debugger do you recommend or is known to work with Cypress software development tools and the FX3?
2. Is is possible to do software development for the FX3 under Ubuntu rather than Windows? if so, what software tools are recommended?
3. Is it possible to use the ARM defined "standard"10 pin, 2x5 configuration, 50 mil pitch connector for the JTAG interface? The more common 20 pin, 2x10 configuration , 0.1" ARM defined JTAG connector is too big for the PCB.
4. Can IAR's Embedded Workbench for ARM (EWARM) be used to develop software for the FX3?
Thanks for your help,
Wayne
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Our application requires following "devices" to be supported on one USB link:
1. One audio device without I2S. Streaming data will be sent and received through the GPIF II interface
2. One SPI device
3. One I2C
4. One UART
Support of items 2,3,4 above will not allow the use of 32 bits on the GPIF II interface. Sixteen bit transfers will be sufficient.
Questions:
1. How is the FX3's 16 Data + UART + SPI + I2S operation mode selected? Software running on the FX3? Hardware?
2. When the 16 Data + UART + SPI + i2S operation mode is selected are GPIOs mapped onto DQ[16} to DQ[27] functional?
3. Can the UART + SPI + GPIF II interfaces be used simultaneously? Of course, transfers on the USB bus can only be for one interface at a time but can the USB Host software "open" all of these interfaces and transfer data as required? Or, will the USB host be forced to "close" one USB device before it "opens" another?
4. When implementing USB bridging functions, how many endpoints are required per bridge? I believe 1 Control Endpoint + 3 (In, Out, Interrupt) is required per bridge. Implementing four USB to UART bridges would require 13 endpoints. One control endpoint shared by all UART bridges plus 12 more endpoints (4 x In, Out and Interrupt endpoints). Is my understand correct?
Thanks for your help,
Wayne
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the fpga eval board referenced in AN84868 is obsolete. Is there an updated version of this app note with an active fpga board?