USB superspeed peripherals Forum Discussions
Hi!
I have the following system: FPGA -> FX3(superSpeed explorer kit)->PC
I send counter from FPGA, but on pc i get shuffled data in multiples of packet size (1024)(1.png in attachments)
I try different parameters of DMA counts, DMA buffer size, but always the same
FX3 work on modified FIFO sync mode(from examples)
I'm not quite sure what other information to provide, so ask, I'll attach
Show LessHi,
I'm trying to debug my FX3 program with J-Link but after download finishes nothing happens. Debugger not didn't stop "main".
At the same time if I try to debug some SDK example program (e.g. UsbUART) it works fine.
Here is J-Link output for my program:
SEGGER J-Link GDB Server V6.96 GUI Version
JLinkARM.dll V6.96 (DLL compiled Feb 19 2021 09:55:51)
-----GDB Server start settings-----
GDBInit file: none
GDB Server Listening port: 2331
SWO raw output listening port: 2332
Terminal I/O port: 2333
Accept remote connection: localhost only
Generate logfile: off
Verify download: on
Init regs on start: on
Silent mode: off
Single run mode: on
Target connection timeout: 5000 ms
------J-Link related settings------
J-Link Host interface: USB
J-Link script: none
J-Link settings file: none
------Target related settings------
Target device: ARM9
Target interface: JTAG
Target interface speed: 1000kHz
Target endian: little
Connecting to J-Link...
J-Link is connected.
Firmware: J-Link EDU Mini V1 compiled Feb 18 2021 11:25:23
Hardware: V1.00
S/N: 801018450
Feature(s): FlashBP, GDB
Checking target voltage...
Target voltage: 3.30 V
Listening on TCP/IP port 2331
Connecting to target...
J-Link found 1 JTAG device, Total IRLen = 4
JTAG ID: 0x07926069 (ARM9)
Connected to target
Waiting for GDB connection...Connected to 127.0.0.1
Reading all registers
Read 4 bytes @ address 0x00000000 (Data = 0xE59FF028)
Received monitor command: speed 1000
Target interface speed set to 1000 kHz
Received monitor command: clrbp
Received monitor command: reset
Resetting target
Received monitor command: halt
Halting target CPU...
...Target halted (PC = 0x00000000)
Received monitor command: regs
PC = 00000000, CPSR = 000000D3 (SVC mode, ARM FIQ dis. IRQ dis.)
R0 = 00000000, R1 = 00000000, R2 = 00000000, R3 = 00000000
R4 = 00000000, R5 = 00000000, R6 = 00000000, R7 = 00000000
USR: R8 =00000000, R9 =00000000, R10=00000000, R11 =00000000, R12 =00000000
R13=00000000, R14=00000000
FIQ: R8 =00000000, R9 =00000000, R10=00000000, R11 =00000000, R12 =00000000
R13=00000000, R14=00000000, SPSR=00000010
SVC: R13=00000000, R14=00000000, SPSR=00000010
ABT: R13=00000000, R14=00000000, SPSR=00000010
IRQ: R13=00000000, R14=00000000, SPSR=00000010
UND: R13=00000000, R14=00000000, SPSR=00000010
Reading all registers
Received monitor command: speed auto
Select auto target interface speed (2667 kHz)
Received monitor command: flash breakpoints 0
Flash breakpoints disabled
Downloading 9512 bytes @ address 0x00000100 - Verified OK
Downloading 16272 bytes @ address 0x40003000 - Verified OK
...
Downloading 16272 bytes @ address 0x40006F90 - Verified OK
Downloading 1688 bytes @ address 0x40030000 - Verified OK
Writing register (PC = 0x40014634)
Read 4 bytes @ address 0x40014634 (Data = 0xE59F1034)
Read 4 bytes @ address 0x00000000 (Data = 0xE59FF028)
Received monitor command: memU32 0xE0052000 = 0x00080014
Writing 0x00080014 @ address 0xE0052000
Received monitor command: sleep 1000
Sleep 1000ms
Reading all registers
Starting target CPU...
And debugger windows shows:
Looks like it really running because I see device is recognized in my windows device manager.
But for some reason in doesn't stop neither at main, nor at any other breakpoint.
I'll greatly appreciate any help here
Things I checked so far:
1) Disabled entering to suspend mode
2) Added CPU frequency change at startup as per KBA229087
Show Less
Hi,
I'm trying to use the watermarks to end the GPIF2 data transfers.
My FX3 design is a 32b slave FIFO with flagA as ready/empty and flagB as watermark (both thread dependent). When accessing the FX3 in RD mode (U2P), the watermark is working as expected and everything goes great.
When accessing in WR mode (P2U), for some reason, the watermark comes earlier than what I would expect. I'm sending a whole FX3 buffer (16KB) from my FPGA and counting the amount of data sent (in 32b words), so for now the watermark flag it is not at the FPGA side.
The watermark for P2U access is configured with a value of 6, so, according to the documentation, the flag should go down when there are 2 samples left to be sent. At the FPGA I'm double registering the watermark, so I'm expecting the watermark to become low when there is no more data to be sent. However I still see that, even after the 2 cycle delay, the watermark does not arrive where I am expecting it.
I'm including the chip scope capture so you can have a look, as well.
The configuration for the FX3 watermark is as follows:
Thanks in advance.
Show LessI have a question about Bulk Out transfer.
Currently I am using Bulk Out transfer to stream data into our logic.
The data to be sent is 0x80100 bytes for each Bulk Out transfer.
The source code of the application is shown below.
int MyXferBulkOut(unsigned char *dt, int length)
{
CCyUSBDevice *USBDevice;
CCyUSBEndPoint *OutEndpt;
bool success;
ULONG ret;
int instance;
USBDevice = s_USBDevice; // USB Device Object, when we are get on initialization.
OutEndpt = USBDevice->EndPointOf(0x02); // BulkOut EP2, Auto DMA, Buffer Count = 4
if (OutEndpt == NULL) {
return(-1);
}
OutEndpt->TimeOut = 5000;
success = OutEndpt->XferData( dt, length ); // length = 0x80100;
if (success) {
ret = 0;
}
else{
ret = -1;
}
return ret;
}
I have some problem.
After executing 0x80 100byte Bulk Out transfer with the XferData function in the above source code, immediately after the function returns
Bulk Out transfer the next 0x80 100byte data.
At this time, the length of data transmitted to our logic circuit is often shorter than expected.
The cause is completely from the EndPoint Buffer of EP2 to our logic circuit immediately after the XferData function returns.
Since it has not been flushed and the XferData function is called again in the above source code in that state,
This is because the previous data remains in the End Point Buffer of EP2 and the next Bulk Out transfer is instructed.
I'm guessing.
I have a few questions.
Q1. Is there any data left in the Endpoint Buffer immediately after the XferData function (BulkOut) returns?
Or does calling the XferData function transfer to EP2-> EP2's Buffer is completely flushed before returning?
Q2. If there is any data left in the EP2 Endpoint Buffer when the XferData function (BulkOut) returns, that is
How to check if it is empty?
Best regards.
Show LessDear sir,
Now I am trying the develop a product with CYUSB3014, and I am reading 2 documents to help me understand it.
<<001-76074_EZ-USB_FX3_Technical_Reference_Manual.pdf>> and <<001-92220_AN75779_How_to_Implement_an_Image_Sensor_Interface_with_EZ-USB_FX3_in_a_USB_Video_Class_UVC_Framework.pdf>>
And I find a problem.
In the chapter 7.11 of Techincal reference manual, there is a flag named DMA_RDY_TH0. And DAM_RDY_TH1.
According to my understand, this flag is used to solve the GPIF's problem between data transfer and the DMA buffer switch in different thead. When the thread is swith to used a free DMA buffer, this flag is used to pause the data transfer.
So if the GPIF used 2 thread to receive the data, this flag should be used.
But in the AN75779, I did not find any information about this flag. So does it mean that there is a loss of data during the 2 thread switch in AN75779 example?
Thanks
Chad
Show LessFiles are attached....
Hi!
I'm looking for an example that streams parallel data back to a PC using the GPIF on an FX3. Does such an example exist? I'm attempting to build an SRAM sniffer.
Thanks!
Show LessHello where can I download the version 1.2.3.3 driver? Online I only see version 1.2.3.20. Thank you.
With Firmware built using Cypress FX3 SDK version 1.3.4 MJPEG frames are corrupted when selecting UVC controls.
Works fine with firmware built using Cypress FX3 SDK version 1.3.1
Show Less