Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

USB superspeed peripherals

Recent discussions

Sort by:
DGates
USB superspeed peripherals
Hello forum,I am looking for some clarification concerning the use of bridged external devices such as IMU sensor, capacitive touch sensor, and PWM LE... Show More
Subhash24
USB superspeed peripherals
Hello,         I want to send vendor-specific commands from the Control center to the Denebola kit, How to do that? and In the control center, I found... Show More
jkhoo
USB superspeed peripherals
Hi FX3 team, From the example code in slavefifo_example\slfifosync, the UART in CyFxSlFifoApplnDebugInit (void) in the example code is pointing to CY_... Show More
amulya_nr
USB superspeed peripherals
Hi I am using FX3 USB superspeed hardware. I am trying to do file transfer from Master to Slave using cyusb_linux application. I have downloaded the l... Show More
Subhash24
USB superspeed peripherals
Hello, I'm using the Denebola kit, I'm trying to write data to SPI flash, I  don't get any error while writing data, but when trying to read back I ge... Show More
TeMa_2997106
USB superspeed peripherals
I'm trying to run FX3 for compliance testing. But It can't enter test mode. Are there any conditions to enter test mode? Also, is there a way to tell ... Show More
rainmen747
USB superspeed peripherals
Is it possible to change DMA configuration while running and restart DMA? Below is a source that runs in 2-socket GPIF mode and runs fine. and I want ... Show More
Flute
USB superspeed peripherals
我使用的开发板是CYUSB3KIT-003。开发板在StreamerExample模式下正常启动后,PC端通过EP0端口给开发板发送一个字节,开发板响应代码如下所示: if(itype == 64 && itarget == 2 && ireq_type==66 && irequest ==... Show More
ThAl_4704151
USB superspeed peripherals
Hello all,  Most of the data I'm trying to transmit seems to be going between the FX3 and the other chip just fine, but I'm periodically getting zero ... Show More
Panneerraja
USB superspeed peripherals
Hi All,  I am using a custom board where Fx3 USB controller is connected to Xilinx FPGA. I am trying to create an board level Vhdl/Verilog test bench ... Show More