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I am attempting to use a MultiChannel DMA with 2 sockets but keep getting `CYU3P_PIB_ERR_THR0_SCK_INACTIVE` and `CYU3P_PIB_ERR_THR1_SCK_INACTIVE` errors. How does the FX3 determine when a thread is active or inactive? We are currently using the GPIF watermark flag to stop data transfer and then our FPGA uses the address bus to switch to the other socket. Would this cause the old (now full of data) socket to become inactive? Do we need to wait for the socket's buffer to empty before switching sockets?
Solved! Go to Solution.
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Hi,
Could you please add some debug prints and share the UART logs? Please make the the following modifications:
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Hi,
This errors may be caused when the FX3 encounters a CY_U3P_USB_EVENT_RESET and CY_U3P_USB_EVENT_SETCONF while transferring data . Please check if you are getting any USB event reset callback.
And you can also refer to this thread:https://community.infineon.com/t5/USB-superspeed-peripherals/GPIF-8-bit-Slave-FIFO-Multichannel-Erro...
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I've added prints to the event handler and I am not getting CY_U3P_USB_EVENT_RESET or CY_U3P_USB_EVENT_SETCONF during streaming and I dont think I am experiencing the same error as the post you linked. When I compile my GPIF project I get a notification that mirror states will be used and 2 warnings that seem like they are not an issue. I am using the 2 bit sync FIFO project as a starting place and the only modifications I have made is remove the ZLP and READ states, changed some of the interface settings and added current_thread watermark and empty flags. The following is my GPIF project build log:
Info: prj.M00013: --------------- Clean Started: 4/3/2023 08:20:20 AM Project: sync_slave_fifo_2bit ---------------
Info: prj.M00016: Deleting file "C:\Users\*removed*\sync_slave_fifo_2bit.cydsn\cyfxgpif2config.h"
Info: prj.M00014: --------------- Clean Succeeded: 4/3/2023 08:20:20 AM ---------------
Info: prj.M00010: --------------- Build Started: 4/3/2023 08:20:20 AM Project: sync_slave_fifo_2bit ---------------
Info: atl.M00066: This project will be built using mirror states and state machine will be modified internally. Do you want to build?
YES
ADD: atl.M00069: warning: Input signal/s 'PKEND' is/are used for the identifying the mirror states and corresponding terms have been removed from outgoing transitions from the state 'IDLE'.
* State Machine ()
ADD: atl.M00069: warning: Input signal/s 'PKEND' is/are used for the identifying the mirror states and corresponding terms have been removed from outgoing transitions from the state 'DSS_STATE'.
* State Machine ()
Info: gpi.M00024: GPIF II module is successfully validated for consistency.
Info: cgn.M00002: Code Generator Module: Output "C:\Users\*removed*\sync_slave_fifo_2bit.cydsn\cyfxgpif2config.h" generated successfully
Info: prj.M00011: --------------- Build Succeeded: 4/3/2023 08:20:23 AM ---------------
Info: prj.M00008: Current project saved successfully
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Hi,
Could you please add some debug prints and share the UART logs? Please make the the following modifications: