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USB superspeed peripherals

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Does Infineon provide the Verilog or VHDL that would go on the Xilinx FPGA to support the CYUSB3035?
I searched through the FX3 webpage and related link starting @ https://www.infineon.com/cms/en/product/universal-serial-bus-usb-power-delivery-controller/periphera...
I also looked through Application Note AN65974 "Designing with the EZ-USB FX3 Slave FIFO Interface" and the associated source files.
I’m looking for the RTL (Verilog or VHDL) for the Spartan FPGA that interfaces to the GPIF interface.

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Moderator 500 solutions authored 1000 replies posted 750 replies posted


Apologies for late response

Please find my comments below:

1. Is the recommendation to use the lower 16 bits in the RTL

>> Yes, DQ[0] - DQ[15] can be used for the 16 bits transfer

The RTL has RESET_N to the CYUSB3035 strapped to ‘1’. To reprogram the FPGA via the USB (App note AN84868), should the reset have an external pull up or an RC to hold off Reset when the FPGA is cleared?

>> The RTL from AN65974 doesn't use RESET (output) from FPGA. Please refer to "Interface Definition" of the GPIF state machine and figure 16 of AN65974. GPIO 59 is driven from the FX3 firmware and not from FPGA. You can modify the logic on FPGA and FX3 firmware according to your application.

PUDC is being pulled low. There are no internal pullups on the FPGA. Is this a correct assumption?

>> Can you please re state this? I didn't understand this

It appears CY8CKIT-003 with an FX3, CYUSB3014, was used with AN65974. Are the reference schematics for CY8CKIT-003 also valid for an FX3S, CYUSB3035? 

>> It seems that there is some misunderstanding here. CY8CKIT-003 is PSOC3 kit, it doesn't use FX3 (CYUSB3014)

There is an output signal PMODE(1 downto 0) from the slaveFIFO2b_fpga_top.vhd that is two bits. The CYUSB3035 has 3 PMODE input bits. To use USB Boot mode (“F11”) and SPI when USB Boot fails mode (“0F1”), should the two PMODE(1 downto 0) be connected to the PMODE[2:1] of the CYUSB3035 and PMODE0 connected to 3.3V?

>> It is not needed that pmode lines should be driven from FPGA. If you want to put switches on the board for PMODE line selection, that can be done.

In the code PMODE is connected to “11” (PMODE <= "11";). If these outputs are left unused, how should the mode pins be strapped

>> You can refer to CYUSB3KIT-003 or Denebola kit schematics for pmode selection

When changing Data bus width from 16 to 32 in GPIF II Designer:

>> Please refer to attached snippets


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