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USB superspeed peripherals Forum Discussions

Anonymous
Not applicable

I have my own custom board with a CYUSB3064-BZXC (CX3 2 lanes). I would like to validate if the super speed design is correct or not. When plugging into a computer, it seems that the device is recognized as USB 2.0.

I have now a strong doubt if I have inverted the RX and TX lanes (the datasheet is very confusing):

cx3-ss.png

When I run the basic firmware bulksrcsink, I see that the packetmaxsize = 512. In the code, I see the following:

    switch (usbSpeed)

    {

    case CY_U3P_FULL_SPEED:

        size = 64;

        break;

    case CY_U3P_HIGH_SPEED:

        size = 512;

        break;

    case  CY_U3P_SUPER_SPEED:

        size = 1024;

        break;

    default:

        CyU3PDebugPrint (4, "Error! Invalid USB speed.\n");

        CyFxAppErrorHandler (CY_U3P_ERROR_FAILURE);

        break;

    }

How can I validate if my design can do super speed or not?

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1 Solution

Hi Gregoire,

1. The trace length should be ok. However, it'll be a problem if you don't place capacitors on SSTX pairs. It is the requirment of USB physicla layer. That should be the root cause according to the clues above.

2. You could use USBtreeview.exe (https://www.uwe-sieber.de/usbtreeview_e.html )

or BUS HOUND(Bus Hound ) to check the response data when host requires device configuration.

View solution in original post

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5 Replies
YangyangC_06
Employee
Employee
50 likes received 25 likes received 10 likes received

Hi Gregoire,

What's P1? Is it a standard USB connector or customized  connector?

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Anonymous
Not applicable
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Ok, you are using the standard USB receptable on your board and standard USB cable which connects your board to PC, correct?

If so, how long is the USB trace from FX3 SSRX/SSTX pins to receptacle. How long is the USB cable?

Have you followed AN70707 to make PCB layout?

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Anonymous
Not applicable

Yes, overall, I have respected everything in the application note:

- chip is side-by-side usb connector on PCB. Everything is routed "correctly".

- cable is 3 inches long (inch not feet)

I have a competitive design with another chip doing super-speed USB camera and I don't have any problem (using same connector, same PCB factory, similar design, etc...)

There is only one thing that I don't have on the Cypress design: I don't have the 2 capacitors in series on the TX lines because the chip is so close to the connector, I didn't have room to put them in between. Does that really matter?

My question was perhaps more: how can I validate super-speed from a software point of view? Does the example that I mentioned above about the max packet size of the firmware bulksrcsink is the best way to validate a super-speed design?

0 Likes

Hi Gregoire,

1. The trace length should be ok. However, it'll be a problem if you don't place capacitors on SSTX pairs. It is the requirment of USB physicla layer. That should be the root cause according to the clues above.

2. You could use USBtreeview.exe (https://www.uwe-sieber.de/usbtreeview_e.html )

or BUS HOUND(Bus Hound ) to check the response data when host requires device configuration.

0 Likes