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USB superspeed peripherals

Anonymous
Not applicable

 Hi,

   

I'm working with the FX3 DVK, following the application notes AN65974 to perform stream_in, stream_out and loopback transfer with my Xilinx FPGA. When performing stream_in and stream_out transfer, it seems quite ok.

   

 

   

However, during loopback transfer, after transfer data out, when I was trying to read data back from bulk in endpoint, it shows that zero length data transfered. I tried to capture how each control signal data react from FPGA side during transfer. I found that sfter SLOE# and SLRD# were both asserted, no data came out from FX3, my FPGA did not recieve any data, flagc and flagd remained 1.

   

 

   

How can I solve this problem?

   

 

   

Regards,

   

Zoe

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1 Reply
Anonymous
Not applicable

 Duplicate post.

   

You can find the response at the original thread:

   

http://www.cypress.com/?app=forum&id=167&rID=110522

   

Regrards,

   

- Madhu Sudhan

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