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Currently, I use FX3 as a bridge for communication between a PC and an external FPGA board as shown below:
read/write FPGA register request
PC ----------------------------------------------> FX3 ------------------------------------> FPGA
read FPGA data request
In this design, FX3 GPIF is a synchronous master and used to:
1. read/write register space from/to FPGA;
2. read data space (FIFO) from FPGA.
The two spaces of the FPGA are distinguished by an adress line of the GPIF interface, e.g. 1 for register space and 0 for data space.
on FX3 side, I tried to use three threads: the first thread (thread0) is used to read register value from the FPGA, the second one for writing FPGA register, and the thrid one for reading FPGA data, so I create three DMA channels as follows:
1.DMA1.prodSckId = 0x0102; 01: GPIF; 02: Thread 2; //for reading FPGA registers
DMA1.consSckId = 0x0302 03: USBOUT; 02: socket number 2 and mapped to end point IN 2;
2.DMA2.prodSckId = 0x0401; 04: USBIN; 01: socket number 1 ; //for writing FPGA registers
DMA2.consSckId = 0x0103 01: GPIF; 03: thread 3;
3.DMA3.prodSckId = 0x0100; 01: GPIF; 00: Thread 0; //for reading FPGA data
DMA1.consSckId = 0x0301 03: USBOUT; 01: socket number 1 and mapped to end point IN 1;
Now, the DMA2 and DMA3 can work well, that is, PC can sucessfully write register to FPGA and read data back from FPGA, but PC can not read FPGA register through DMA1 channel.
My question is that, if FX3 GPIF as a synchronous master, can more than one thread be used to transfer data from outside to FX3 engress end points? or there are any configuration errors in the DMA channel creation?
Your suggestions are very appreciated!
Scott
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Hello,
Please refer to AN65974 app note https://www.cypress.com/file/136056/download to understand about the DMA flags and their latencies.
Also, refer to this thread does DMA_RDY_TH0 has latency? - Cypress Developer Community
Rashi