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Hi All,
I use FX3 be my USB3.0 bridge FIFO. I have verified the firmware of FX3 in CYUSB3KIT-003(slave) and MCU-EVB(host) by P-port(asynchronous sram). When I migrate EVM in another application platform, I found some different reaction of my new platform(change from CYUSB3014 to CYUSB3013, Clock from 19.2Mhz to 26Mhz).
I found if I write 0x0800 to PP_DRQR5_MASK(0x89), PP_INTR_MASK will be changed to 0x08B8. Once I got the data from my computer, the data always separated.
For example, when I use CyControl.exe to send a number string. 01234567890123456789. I always got 010123 only 6 digit and not number. Then PP_SOCK_STAT_L become to 0x0001.
I also check PP_ERROR, the value return is 0x15 in the meantime. Do anyone have idea why change PP_INTR_MASK when I set PP_DRQR5_MASK?
T.L.
Solved! Go to Solution.
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Hello,
Please let me know more details:
I found if I write 0x0800 to PP_DRQR5_MASK(0x89), PP_INTR_MASK will be changed to 0x08B8.
>> Please let me know why and where did you change the value. Was the PP_DRQR5_MASK values the same in the previous environment (CYUSB3014)
I always got 010123 only 6 digit and not number. Then PP_SOCK_STAT_L become to 0x0001.
>> Please confirm if the GPIF bus width is changed to 16 bits when you moved to CYUSB3013.
>> How do you check PP_SOCK_STAT_L. If possible please share your firmware. It will help us to debug.
>> Can you share the control center snippet after you do and IN transfer
Regards,
Rashi
Rashi
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Hello,
Please let me know more details:
I found if I write 0x0800 to PP_DRQR5_MASK(0x89), PP_INTR_MASK will be changed to 0x08B8.
>> Please let me know why and where did you change the value. Was the PP_DRQR5_MASK values the same in the previous environment (CYUSB3014)
I always got 010123 only 6 digit and not number. Then PP_SOCK_STAT_L become to 0x0001.
>> Please confirm if the GPIF bus width is changed to 16 bits when you moved to CYUSB3013.
>> How do you check PP_SOCK_STAT_L. If possible please share your firmware. It will help us to debug.
>> Can you share the control center snippet after you do and IN transfer
Regards,
Rashi
Rashi
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Hi Rashi,
I just use sample code and GPIFII Designer to assemble project please see the .zip file. You can see GPIF bus is 16 bit.
I set DMA enable, long transfer and socket first.
val = (DMA_ENABLE | LONG_TRANSFER | sck); // sck=3
IOWR_REG16(PP_DMA_XFER, val);
then write 0x0800 to PP_DRQR5_MASK.
And just polling polling PP_SOCK_STAT_L and check socket 3 is incoming.
My part of MCU code:
if(0x81 == IORD_REG16(PP_IDENTIFY) )
{
IOWR_REG16(PP_DMA_XFER, 0x0503);
wait_us(50);
/* write to PP_DMA_XFER to configure transfer socket number, rd/wr operation, and long/short xfer modes */
val = (DMA_ENABLE | LONG_TRANSFER | sck); //sck = 3
IOWR_REG16(PP_DMA_XFER, val);
/* Poll for DMA_READY_EV */
count = 10000;
do {
val = IORD_REG16 (PP_EVENT);
wait_us(10);
count--;
} while ((!(val & DMA_READY_EV)) && (count != 0));
if (count == 0) {
printk("DMA_READY_EV Fail timeout; Count = 0\n",);
return false;
}
/* enable DRQ WMARK_EV for DRQ assert */
IOWR_REG16(PP_DRQR5_MASK, DMA_WMARK_EV);
wait_us(50);
}
if(9 == IORD_REG16(PP_SOCK_STAT_L) )
{
uint16_t data_ret[512], buf_sz = 512;
sz = IORD_REG16(PP_DMA_SIZE);
printf("PP_DMA_SIZE=%2X\r\n", sz);
count=0;
do {
for (i = 0; i < (buf_sz / 2); i++)
{
data_ret = IORD_REG16( (uint16_t*) i );
}
count += (buf_sz / 2); /* count in words */
if (count < (sz/2))
do {
udelay(10);
val = IORD_REG16 (PP_SOCK_STAT_L);
} while(!(val&(0x1<<sck)));
} while (count < (sz/2));
for (int i = 0; i < (sz/2 + 1); ++i)
{
printf("PP_DMA_SIZE=%2X\r\n", val);
}
}
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Hello,
I didn't find the .zip file in the attachment. Please share the .zip file.
Also, can you share the snippet of the control center when you get 010123 only 6 digits and not the number.
Regards,
Rashi
Rashi
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Hi Rashi,
I solved my problem. It's my host code got some bug. Thank you for your help.