I have some problem about vsync and hsync on FX3

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arLi_4711941
Level 1
Level 1

my camera only get one frame data. when I get GPIF status through cyu3pgpifgetsmstate. I find the value is PARTIAL_BUF_IN_SCK0. But When I use OV5640, I find the value is WAIT_FOR_FRAME_START_0 or WAIT_FOR_FRAME_START_1.  My camera is different from OV5640  about Hsync and Vsync . My camera is that the last Hsync is low and Vsync is low at the same time, Vsync is high and the first Hsync is high at the same time. Hsync and Vsync all is that high active.

How can I analyse this problem . what is FW_TRG about GPIF state Machine?

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YashwantK_46
Moderator
Moderator
Moderator
100 solutions authored 50 solutions authored 50 likes received

Hello,

Can you please elaborate more about, "My camera is that the last Hsync is low and Vsync is low at the same time, Vsync is high and the first Hsync is high at the same time. Hsync and Vsync all is that high active."  ?

The FW_TRG is used by the firmware to trigger a software interrupt to the GPIF state machine to give the control back to the GPIF state machine.

In the FULL_BUF_IN_SCK or PARTIAL_BUF_IN_SCK, there is an INTR_CPU action which causes the control to transfer to the firmware to handle the header addition and the partial buffer wrapup (in case of PARTIAL_BUF_IN_SCK) stage.

Once these actions are completed, the firmware triggers an interrupt to the GPIF state machine using CyU3PGpifControlSWInput() API by firstly setting it to CyTrue (FW_TRG is asserted) to make the transition to FRAME_END_SCK state in the state machine and then setting the API to CyFalse (FW_TRG is de-asserted) to transition to IDLE_SCK state to take care of the next incoming frame.

Regards,

Yashwant

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YashwantK_46
Moderator
Moderator
Moderator
100 solutions authored 50 solutions authored 50 likes received

Hello,

Can you please elaborate more about, "My camera is that the last Hsync is low and Vsync is low at the same time, Vsync is high and the first Hsync is high at the same time. Hsync and Vsync all is that high active."  ?

The FW_TRG is used by the firmware to trigger a software interrupt to the GPIF state machine to give the control back to the GPIF state machine.

In the FULL_BUF_IN_SCK or PARTIAL_BUF_IN_SCK, there is an INTR_CPU action which causes the control to transfer to the firmware to handle the header addition and the partial buffer wrapup (in case of PARTIAL_BUF_IN_SCK) stage.

Once these actions are completed, the firmware triggers an interrupt to the GPIF state machine using CyU3PGpifControlSWInput() API by firstly setting it to CyTrue (FW_TRG is asserted) to make the transition to FRAME_END_SCK state in the state machine and then setting the API to CyFalse (FW_TRG is de-asserted) to transition to IDLE_SCK state to take care of the next incoming frame.

Regards,

Yashwant

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