Hello,
If you are using 100MHz clock and 32 bit interface, theoretically, you should be seeing a data rate of around 400MBps. But, as you might b]e knowing, Slave FIFO interface makes use of DMA flags to understand if the DMA buffers are full/empty to perform the write/read operations. Also, there is a latency involved in switching from one DMA buffer to another. Due to this, you will not be able to achieve the 400MBps throughput using this interface. Please refer to Section 11.5.2 - Steps to test streaming transfers of AN65974 to understand the data rate obtained at our end while testing:
https://www.infineon.com/dgdl/Infineon-AN65974_Designing_with_the_EZ-USB_FX3_Slave_FIFO_Interface-Ap...
As you can see, the data rate obtained is less than the max data rate (400MBps).
Using ping pong buffers as used in AN75779 for Slave FIFO interface is not a suitable method. This is because of the following reasons:
1. Slave FIFO interface makes use of address lines to select the threads. Where as the ping pong mechanism used in AN75779 makes use of the GPIF II state machine to select the thread for sampling the incoming data.
2. Slave FIFO interface makes use of DMA flags to indicate the availability of a DMA buffer for data transfer. But, AN75779 makes use of GPIF II counters for tracking the availability of space within a DMA buffer.
So, these two interfaces (i.e FV LV interface used in AN75779 and Slave FIFO) are quite different and should not be mixed. You can define a custom interface similar to FV LV interface used in AN75779. You can then configure the FPGA to follow the interface defined. After this, you can build your own GPIF II state machine by using the state machine in AN75779 as a reference to receive the data from the FPGA.
Best Regards,
Jayakrishna
