How to use fx3 to continuously acquire data generated by ADC

[vgegok]

When I try to use the "sync slave fifo" interface of cyusb3014 to continuously and instantaneously transmit the sampled data generated by the ADC to the PC, I'm stuck with the following problems:
1. The data I receive after reaching MaxPktSize will be lost for a period of time (about 42 cycles data loss), the following is my test using a counter as data:

It can be seen that the data is missing after 0x3917B759:

2. When I read the data, there are always expired data being read to the PC instead of real-time data. These data have expired for the ADC. As shown in the above picture, triggered data can be read only when I need to click the "Transfer Data-IN" multiple times after triggering the waveform .
I hope to get the current data of the ADC when I press "Transfer Data-IN".

[AliAsgar]

Hi

1. Make sure the host is fast enough to read the data from the device. Flag is asserted only when there is a free buffer to receive the data. Please let us know the DMA buffer size, buffer count and MaxPacketSize. Also let us know if there any changes to the default state machine.

2. You could configure a control signal, which is set when a vendor command is sent through my the control center.  Send the vendor command, when the sampling of ADC is needed.

Modify the state machine such that the GPIF lines are written only when the control signal is set.

Best Regards,

AliAsgar

[vgegok]

I used the code in AN65974 and AN84868 without making any changes.

Also referred to Reading-data-from-an-ADC  ，I try to use D:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\firmware\basic_examples\cyfxgpiftousb,  but I got the same problem：

[AliAsgar]

Hi,

Could you try setting the DMA buffer size as 32*1024 and DMA buffer count as 2 and check if the issue is seen?

Best Regards,
AliAsgar

[vgegok]

Thank you for your reply! 

According to your suggestion, I modified the following code:

cyfxgpiftousb.c

 /* Create the channels used for loop-back function. */
    dmaCfg.size           = 1024 * 32;
    dmaCfg.count          = 2;
    dmaCfg.prodSckId      = CY_FX_LOOP_PRODUCER_SOCK;
    dmaCfg.consSckId      = CY_U3P_CPU_SOCKET_CONS;
    dmaCfg.dmaMode        = CY_U3P_DMA_MODE_BYTE;
    dmaCfg.notification   = CY_U3P_DMA_CB_PROD_EVENT;
    dmaCfg.cb             = LoopBackDmaCallback;
    dmaCfg.prodHeader     = 0;
    dmaCfg.prodFooter     = 0;
    dmaCfg.consHeader     = 0;
    dmaCfg.prodAvailCount = 0;
    apiRetStatus = CyU3PDmaChannelCreate (&glLoopOutChHandle, CY_U3P_DMA_TYPE_MANUAL_IN, &dmaCfg);
    if (apiRetStatus != CY_U3P_SUCCESS)
    {
        CyFxAppErrorHandler (apiRetStatus);
    }

    apiRetStatus = CyU3PDmaChannelSetXfer (&glLoopOutChHandle, 0);
    if (apiRetStatus != CY_U3P_SUCCESS)
    {
        CyFxAppErrorHandler (apiRetStatus);
    }

    dmaCfg.size           = 1024 * 32;
    dmaCfg.count          = 2;
    dmaCfg.prodSckId      = CY_U3P_CPU_SOCKET_PROD;
    dmaCfg.consSckId      = CY_FX_LOOP_CONSUMER_SOCK;
    dmaCfg.dmaMode        = CY_U3P_DMA_MODE_BYTE;
    dmaCfg.notification   = 0;
    dmaCfg.cb             = 0;
    dmaCfg.prodHeader     = 0;
    dmaCfg.prodFooter     = 0;
    dmaCfg.consHeader     = 0;
    dmaCfg.prodAvailCount = 0;
    apiRetStatus = CyU3PDmaChannelCreate (&glLoopInChHandle, CY_U3P_DMA_TYPE_MANUAL_OUT, &dmaCfg);
    if (apiRetStatus != CY_U3P_SUCCESS)
    {
        CyFxAppErrorHandler (apiRetStatus);
    }

    apiRetStatus = CyU3PDmaChannelSetXfer (&glLoopInChHandle, 0);
    if (apiRetStatus != CY_U3P_SUCCESS)
    {
        CyFxAppErrorHandler (apiRetStatus);
    }

cyfxgpiftousb.h

/* Burst mode definitions: Only for super speed operation. The maximum burst mode 
 * supported is limited by the USB hosts available. The maximum value for this is 16
 * and the minimum (no-burst) is 1. */

/* Burst length in 1 KB packets. Only applicable to USB 3.0. */
#ifndef CY_FX_EP_BURST_LENGTH
#define CY_FX_EP_BURST_LENGTH           (16)
#endif

/* Size of DMA buffers used by the application. */
#ifndef CY_FX_DMA_BUF_SIZE
#define CY_FX_DMA_BUF_SIZE              (1024*32)
#endif

/* Number of DMA buffers to be used on the channel. */
#ifndef CY_FX_DMA_BUF_COUNT
#define CY_FX_DMA_BUF_COUNT             (2)
#endif

But the problem still hasn't been solved.

[AliAsgar]

Hi,

Why are there two channels, MANUAL_IN and MANUAL_OUT. Can a single AUTO DMA channel be created from the PIB socket to the USB?
Is there any particular application requirements to have such a DMA structure, if yes please let us know the application.

Best Regards,
AliAsgar

[vgegok]

I used the cyfxgpiftousb example without making changes.

I use FPGA to obtain the data of ADC. My ADC is 12 bits/200MHz. I expand the data to 16 bits, stack the data into 32 bits twice, and then send it to FX3 through 100MHz/32bit FIFO interface.

I hope that PC can obtain ADC data in real time and uninterruptedly.

Best Regards,

Vgegok

[vgegok]

I'm not very familiar with the development of FX3, but I think my requirements are the most basic and simple.
These two problems have tortured me for two weeks. I hope it can be solved quickly. It is better to use slaveFIFO (AN65974) to make simple modifications.

[vgegok]

Can you help me?

Thanks!

vgegok

[AliAsgar]

Hi vgegok,

It would be better to use the slaveFIFO (AN65974) firmware for your use case. FX3 provides flags for flow control. Make sure that the FPGA transfers data based on the flag status.

Also note that the host application should be fast enough to read data from the device, so that the flags are not asserted for long time denoting unavailability of DMA buffers.

Best Regards,
AliAsgar

[vgegok]

Thanks for your reply! 

In the FPGA code of AN65974, the data written to FX3 does not change all the time like my ADC. Instead, the data is accumulated only when the FX3 flag is detected. Therefore, the received data will not be discontinuous, but the accumulated count that is not affected by the flag bit will be interrupted.
In addition, I used 50MHz to write 32-bit data and got the same problem.

vgegok

[AliAsgar]

Hi vgegok,

If flow control is not required and continuous data needs to be sent to the host from FX3, a custom interface can be created as per the application using ping pong DMA buffer architecture as mentioned in the UVC application note (AN75779). Ping Pong DMA buffer structure provides slightly better performance than the standard DMA structure.

Best Regards,
AliAsgar

[vgegok]

I have a question. Does the "FIFO" used in "SyncSlaveFifo" support simultaneous writing and reading?
I think this FIFO does not support simultaneous write and read, because if it does, when I reduce the write rate, the PC reads the data through USB in a timely manner, and the FIFO will not be full.
But now, no matter how slow the data is written, the fifo flag bit (FLAGA and FLAGB) will be triggered.
I want to make sure that my understanding is correct?

Thanks!

vgegok

[AliAsgar · Accepted solution]

Hi vgegok,

FIFO in the SyncSlaveFIFO does not support explicit simultaneous reading and writing. However, as I mentioned in the previous post, ping-pong DMA buffers can be used to virtually simultaneously read the buffer from the USB and write another buffer from the GPIF.

Please refer to the UVC GPIF state machine in the AN75779 application note. There is continuous streaming of data without any flow control.

Best Regards,
AliAsgar