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USB superspeed peripherals Forum Discussions

wexi_4711301
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5 replies posted 5 sign-ins First reply posted

Hello,

We have designed our own board: AD->FPGA->FX3. We capture data using AD and send the sampling data to fx3 via FPGA. We followed the application note AN65974 using 16 bits width GPIF interface and set the watermark to 3. While we transmitted the data to fx3, the DMA buffer is full and the flagb goes low periodically. Then the data transmission paused and the continuously input sampling data got lost. Please see the attached file. I want to know how to stream in the samples without losing data, using two DMA buffers? two threads? It seems that sampling the state of flags will cause latency too. Please give me some advise. 

flag_trig.JPG

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Hemanth
Moderator
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First like given First question asked 750 replies posted

Hi,

We have a GPIF state machine in which flags are not output to FPGA and address pins are not used for thread selection - instead, data can be written alternatively between two threads - 0 and 1.

More details can be understood by going through the attached state machine.

Using this state machine, in the firmware, a Multichannel can be created with 2 PIB sockets (mapping to thread 0 and 1) as producers and USB as consumer.

Even with this model, there will be few clock cycles on the slave fifo interface where FX3 is not sampling the data (that is between STATE3 and STATE6). If this is also not desired, then necessary modifications can be done to the state machine.

Regards,

Hemanth

Hemanth

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wexi_4711301
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5 replies posted 5 sign-ins First reply posted

no one has the same issue?

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wexi_4711301
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5 replies posted 5 sign-ins First reply posted

Would any Cypress engineer answer this problem? Thanks

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Hemanth
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First like given First question asked 750 replies posted

Hi,

From your comments, what I understand is that you are trying to avoid the pause in data transmission between FX3 and FPGA. You want that to be continuous.

If this is the case, I don't think you need flow control and hence you can check the state machine in https://www.cypress.com/documentation/application-notes/an75779-how-implement-image-sensor-interface...

where data is sent from sensor to FX3 through two threads 0 and 1 alternatively.

Regards,

Hemanth

Hemanth
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Hi Hemanth,

Thank you for your kind reply. I have read the document you provided above. However, this is for video streaming and is difficult for me to modify the code to meet our requirement. Is there any  simple demo to show how to implement the two threads switching without loss of data? I really appreciate your assistance.

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Hemanth
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First like given First question asked 750 replies posted

Hi,

I am looking internally if we have an example project for your requirement.

Can you please confirm that you do not need flow control between FPGA and FX3.

Regards,

Hemanth

Hemanth
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Hemanth
Moderator
Moderator
Moderator
First like given First question asked 750 replies posted

Hi,

We have a GPIF state machine in which flags are not output to FPGA and address pins are not used for thread selection - instead, data can be written alternatively between two threads - 0 and 1.

More details can be understood by going through the attached state machine.

Using this state machine, in the firmware, a Multichannel can be created with 2 PIB sockets (mapping to thread 0 and 1) as producers and USB as consumer.

Even with this model, there will be few clock cycles on the slave fifo interface where FX3 is not sampling the data (that is between STATE3 and STATE6). If this is also not desired, then necessary modifications can be done to the state machine.

Regards,

Hemanth

Hemanth
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