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USB superspeed peripherals Forum Discussions

jnagy
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I am using GPIF to communicate with an FPGA but am experiencing issues where the firmware is staying in the reset state without logging any errors. Due to no state changes, I believe the issue may be with the clock being used and want to get some help verifying that I have the correct firmware configuration. In GPIF I am using the "External" clock setting and my understanding is that the FX3 supports up to a 100MHz clock and simply needs to be connected to GPIO 16 to work. Is this correct? Is any other configuration needed? My PIB clock init is as follows:

pibclock.clkDiv      = 2;
pibclock.clksrc=CY_U3P_SYS_CLK;
pibclock.isDllEnable = CyFalse;
pibclock.isHalfDiv   = CyFalse;

And the device clock is configured as follows:

clockConfig.setSysClk400  = CyFalse;
clockConfig.cpuClkDiv     = 2;
clockConfig.dmaClkDiv     = 2;
clockConfig.mmioClkDiv    = 2;
clockConfig.useStandbyClk = CyFalse;
clockConfig.clksrc=CY_U3P_SYS_CLK;

I am using a 16-bit data bus.

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Rashi_Vatsa
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Hello,

The external clock from FPGA needs to be connected to the PCLK pin if FX3 (GPIO 16)

No changes need to be done in the firmware if the external clock is changed other than choosing the external clock option in the GPIF II Designer Tool

Also, please confirm if the external clock is provided to FX3 after the PIB block is initialized

Regards,
Rashi
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The FPGA  provides the clock before the PIB block is initialized with the CyU3PPibInit function. While the clock is getting set up the FX3 chip's reset signal is asserted and then once the clock is stable the FX3 is allowed to start. Could this cause a problem?

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Rashi_Vatsa
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Hello,

We have seen similar issues before. For debugging further, is it possible to start the external clock after the PIB block is initialized?

To narrow down the problem, you can also try using default SlaveFIFO example from AN65974 with your FPGA and check if the GPIF II state changes

Regards,
Rashi
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Loading a modified version of the AN65974 to add another thread to output the state of the state machine shows that the state machine does advance into the IDLE and DSS_STATE states.

Using a FPGA with a clock enable, after the PIB is loaded I can see the state machine going between IDLE and DSS_STATE states with a few ZLP and WRITE state prints. However the firmware doesnt seem to be registering all actions in the GPIF state machine. I have a INTR_CPU action in each non-RESET state so I can use the registered callback to count the number of times I enter each state however when I run the firmware I can see the debug prints showing switching between IDLE and DSS_STATE and occasionally WRITE states but the only state counters that change is IDLE's counter by 2. No other counter ever increments. The state machine also returns that it is in state 7 however looking at the cyfxgpif2config.h state defines it only goes up to 6. I am not sure where state 7 is coming from. I have included my firmware so you can see the state machine and counters.

Is there any specific reason why the PIB needs the PCLK provided after the PIB has been initialized or why these calls sometimes fail? Also I cant find anywhere in the TRM or datasheet that states the PCLK should be provided only after CyU3PPibInit has been run.

Is it possible to get an example FPGA bitfile that we can compare ours to to make sure we are sending signals to the FX3 properly?

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Rashi_Vatsa
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Hello,

 The state machine also returns that it is in state 7 however looking at the cyfxgpif2config.h state defines it only goes up to 6. I am not sure where state 7 is coming from. I have included my firmware so you can see the state machine and counters.

>> This is strange. Please share the UART debug prints when this issue is seen.

Is there any specific reason why the PIB needs the PCLK provided after the PIB has been initialized or why these calls sometimes fail? Also I cant find anywhere in the TRM or datasheet that states the PCLK should be provided only after CyU3PPibInit has been run

>> We recommend to program FX3 before FPGA is ready to send the data. Please refer to section 12.5 of AN65974 for the steps for testing

Is it possible to get an example FPGA bitfile that we can compare ours to to make sure we are sending signals to the FX3 properly?

>> Please refer to FPGA source files in AN65974.zip from application notes section of this page https://www.infineon.com/cms/en/product/universal-serial-bus-usb-power-delivery-controller/periphera... 

Regards,
Rashi
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I have included the log file (state_7_log.txt) which contains the UART printout where the state machine enters state 7. I have also included the firmware and GPIF model used. I included 2 log files, one with status prints every 5000 ticks and another with prints every 2250 ticks. Going off of the 2250 tick logs it seems like the state machine is entering state 7 regularly. In cyfxgpif2config.h there are only state defines for 0 through 6.

Could there be something wrong with the clock setup? If I have "pibclock.clkDiv = 4" and "clockConfig.setSysClk400 = CyFalse", would this create 96MHz clock vs a 100.8MHz clock with "clockConfig.setSysClk400 = CyTrue"?

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Rashi_Vatsa
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Hello,

Could there be something wrong with the clock setup? If I have "pibclock.clkDiv = 4" and "clockConfig.setSysClk400 = CyFalse", would this create 96MHz clock vs a 100.8MHz clock with "clockConfig.setSysClk400 = CyTrue"?

>> This looks fine

 logs it seems like the state machine is entering state 7 regularly. In cyfxgpif2config.h there are only state defines for 0 through 6.

>> Can you please print smstate directly (not passing it to getGpifStateString) after CyU3PGpifGetSMState and let me know if 7 is still seen. 

The state machine has mirror states but 7 is not a mirror state. To know more about mirror states, please refer to FX3 TRM

Regards,
Rashi
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After modifying the SM state print I am still seeing state 7 in the logs. I have included an updated log file. 

Is there any resources which summarize how the pins on the FPGA connect to the pins on the FX3 for the AN65974 example? I'd like to check the pin connections between the FPGA and FX3 and compare them to my own.

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Rashi_Vatsa
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Hello,

After modifying the SM state print I am still seeing state 7 in the logs. I have included an updated log file

>> This is strange. Please let me know if FPGA is driving SLCS and PKTEND when this test is done. The reason is that in the logs i see gpif states as 6,1, and 5. To narrow down the issue, please remove INTR_CPU from the states as this will be called multiple times as "Repeat actions until next transition" is checked. This will cause interrupts at every clock cycle. Please check if state 7 is seen when INTR_CPU is removed or "Repeat actions until next transition" is unchecked.

Please refer to table 2 of AN65974 and the GPIF state machine in the AN65974.zip for the interface signals

Regards,
Rashi
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I have included 2 log files, one with the repeat actions box unchecked on all states and a second with interrupt actions removed from all states except SHORT_PKT (state 4) and ZLP (state 5). Both still enter state 7.

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Rashi_Vatsa
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Hello,

Please let me know if the same issue is seen with CYUSB3KIT-003 (FX3 SuperSpeed explorer kit)

Please check the hardware connections and the PCLK 

Regards,
Rashi
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I cannot run my firmware on the FX3 Explorer kit because it lacks the GPIF - FPGA connections and state machine driver FPGA bitfile. When I upload my firmware to that board, it activates successfully but doesn't register any inputs when I open the windows camera app. On my hardware that triggers a stream start and the state machine activates.

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Rashi_Vatsa
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Hello,

If the clock from FPGA is stable, the GPIF states will change based on the inputs from the FPGA. As per our discussion, the GPIF state machine was stuck, and it goes to states which are not there in the header file. 

As mentioned earlier as the issue seems on the FPGA - GPIF interface, we would recommend checking the hardware connections and the if the clock is stable

Regards,
Rashi
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I've now checked the PCLK pin and it is stable with PCLK supplied after the FX3's PIB block had been initialized. Our FPGA is driving the PCLK pin using IOstandard LVCMOS33  (within power domain V_IO1's 1.7-3.6V requirement) with a drive strength 12mA. I found some PCLK jitter requirements (Table 12) in the datasheet and we are within those specs too.

With the bulk endpoint of cyfxgpiftousb still not working with an external GPIF PCLK, I don't think I can trust any of the control signals that would be coming from our FPGA. Are there any other clock requirements that I have missed? They seem to be spread throughout the datasheet, TRM and hardware design guideline documents.

Also while the cyfxgpiftousb's Endpoint 1 doesn't produce any data with the external PCLK, I can use Endpoint 2 to send data to the FX3 and then read back from Endpoint 3 with an external PCLK. I am not sure if loopback uses PCLK but figured I should say so in case it matters.

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jnagy
Level 3
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25 replies posted 25 sign-ins 10 replies posted

While looking through our schematic I found that the PCLK pin had a 33.2 ohm termination resistor instead of a 22 ohm resistor. I will be replacing that and retesting. Could this resistor cause the clock to not get recognized by the FX3? Also, are termination resistors required on all GPIF lines (my PCB currently only has 1 termination resistor on PCLK)? Looking in the hardware design guidelines it reads like there should but it never outright says all GPIF address, data and control lines must have these resistors.

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Rashi_Vatsa
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Hi,

Please find my comments below:

- Loopback in GPIFtoUSB example doesn't use PCLK

- Yes, we recommend 22ohm termination resistors on GPIF lines. The reflection phenomenon occurs due to impedance mismatch of GPIF lines and also due to the PCB stack up. Therefore, you must use 22-Ω series termination resistors to avoid reflection on these lines.

If the GPIF lines are routed >5 inch , we recommend doing signal integrity simulation using the  FX3 IBIS model, and come up with a termination. 

- Please refer to table 9 of datasheet and the KBA for drive strength range.  FX3/FX3S: I/O Drive Strength – KBA232794 - Infineon Developer Community

If possible , please capture a trace (near to FX3 pint) of PCLK

Regards,
Rashi
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