How to set pin list on CYUSB3014

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jnagy
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I have a device with an CYUSB3014 and am trying to connect the UART to an FPGA to access the prints from the firmware. Due to limitations on the hardware, the UART is connected to GPIO 48 and 49 so I am trying to use the "16-bit Data Bus + UART + SPI + I2S" pin configuration listed in Table 7 of the FX3 datasheet however I seem to be getting inconsistent output with the following settings (meaning when I try these setting I get no output sometimes):

 

io_cfg.isDQ32Bit = CyFalse;                        /* 16-bit bus */
io_cfg.useUart   = CyTrue;                         /* For logging */
io_cfg.useI2C    = CyFalse;
io_cfg.useI2S    = CyFalse;
io_cfg.useSpi    = CyFalse;
io_cfg.lppMode   = CY_U3P_IO_MATRIX_LPP_UART_ONLY; /* Required mode for 16-bit bus w/ UART */
io_cfg.s0Mode    = CY_U3P_SPORT_INACTIVE;
io_cfg.s1Mode    = CY_U3P_SPORT_INACTIVE;
io_cfg.gpioSimpleEn[0]  = 0;                       /* No GPIOs are enabled. */
io_cfg.gpioSimpleEn[1]  = 0;
io_cfg.gpioComplexEn[0] = 0;
io_cfg.gpioComplexEn[1] = 0;

 

However if I set "CY_U3P_IO_MATRIX_LPP_UART_ONLY" to "CY_U3P_IO_MATRIX_LPP_DEFAULT" I do get prints consistently. I have 2 questions:

1. How do I ensure I have the correct pin config (according to Table 7 of the FX3 datasheet)? I assume it is through the useUart, useI2C, useI2S, useSpi and isDQ32Bit properties but I can't find any documentation that confirms this.
2. What is the difference between "CY_U3P_IO_MATRIX_LPP_UART_ONLY" and "CY_U3P_IO_MATRIX_LPP_DEFAULT"? In reading the enum documentation it seems like I should have "CY_U3P_IO_MATRIX_LPP_UART_ONLY" since I have a 16-bit bus with only UART enabled.

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1 Solution
JiangJing
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Hi,

     1,For I/O Matrix Configuration, you can refer to chapter 4 of FX3_TRM(Cypress/EZ-USB FX3 SDK/1.3/doc/firmware);

2, CY_U3P_IO_MATRIX_LPP_DEFAULT:  Default LPP mode where all peripherals are enabled.
CY_U3P_IO_MATRIX_LPP_UART_ONLY :  LPP layout with GPIF 16-bit and UART only.

In FX3  chip, SPI, UART, and I2S interfaces are multiplexed on the serial peripheral port. UART lines can be routed either on GPIO[46]-GPIO[49] or on GPIO[53]- GPIO[56] pins of FX3. When you are selecting the LPP mode as UART_ONLY the UART pins will be routed to GPIO[53]- GPIO[56] .

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JiangJing
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First like given 250 sign-ins 250 replies posted

Hi,

     1,For I/O Matrix Configuration, you can refer to chapter 4 of FX3_TRM(Cypress/EZ-USB FX3 SDK/1.3/doc/firmware);

2, CY_U3P_IO_MATRIX_LPP_DEFAULT:  Default LPP mode where all peripherals are enabled.
CY_U3P_IO_MATRIX_LPP_UART_ONLY :  LPP layout with GPIF 16-bit and UART only.

In FX3  chip, SPI, UART, and I2S interfaces are multiplexed on the serial peripheral port. UART lines can be routed either on GPIO[46]-GPIO[49] or on GPIO[53]- GPIO[56] pins of FX3. When you are selecting the LPP mode as UART_ONLY the UART pins will be routed to GPIO[53]- GPIO[56] .

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