How to set GPIFII detect rising edge

[Wellington]

Hello
Is there a way to detect rising edge of FV instead of detect it on high state?

I have a application where we could not relies on the FV high, but it need to relies on FV rising edge. Any possible way to detect this?

Thanks

[Rashi_Vatsa · Accepted solution]

Hello,

FV will be sampled on the clock edge (if using GPIF in synchronous mode). If the value of FV is detected as more than the minimum VIH value, the transition equation will be true.

 GPIF II Designer tool does not have options for edge detection for an input signal in the transition equation dialog box.  

[Wellington]

Hello Rashi,

We have an issue where the image get combined if the Image size is more than 4MB.
I am running window10 x64, with driver 1.2.3.25. (Unsigned version), CYAPI. API are called with Xferdata()
Image size: 2048x2048x2

The combined row is quite random, as long as the image size is more than 4MB, then we get a combined image from previous frame to current frame.
Host would not send frame request whereas the FPGA will keep on sending frame to FX3. So we only calling on Xferdata()  to received frame. We have checked on the FPGA side the data is clean.
Tested the same with different image size 4096x512x2 or 512x512x2 is fine.

We are using the dual buffer state machine. Ist possible the state machine error on this?

DMA setup:
//Create a DMA MULTI channel for sending the video data to the USB host.
CyU3PMemSet((uint8_t *)&dmaCfg, 0, sizeof(dmaCfg));
dmaCfg.size = 16*1024;//burstLength*size;//16* size; //16*1024
dmaCfg.count = 5; //6 //5
dmaCfg.validSckCount = 2;
dmaCfg.prodSckId[0] = (CyU3PDmaSocketId_t)CY_U3P_PIB_SOCKET_0;
dmaCfg.prodSckId[1] = (CyU3PDmaSocketId_t)CY_U3P_PIB_SOCKET_1;
dmaCfg.consSckId[0] = (CY_U3P_UIB_SOCKET_CONS_3);
dmaCfg.prodAvailCount = 0;
dmaCfg.prodHeader = 0;
dmaCfg.prodFooter = 0;
dmaCfg.consHeader = 0;
dmaCfg.dmaMode = CY_U3P_DMA_MODE_BYTE; //CY_U3P_DMA_MODE_BUFFER
dmaCfg.notification = CY_U3P_DMA_CB_PROD_EVENT| CY_U3P_DMA_CB_CONS_EVENT;
dmaCfg.cb = CyFxApplnDmaCallback;
apiRetStatus = CyU3PDmaMultiChannelCreate(&glChHandleMultiCh,
CY_U3P_DMA_TYPE_AUTO_MANY_TO_ONE, &dmaCfg);
if (apiRetStatus != CY_U3P_SUCCESS)
{
CyFxAppErrorHandler(apiRetStatus);
}

Thanks

[Rashi_Vatsa]

Hello, 

I understand that you are using SlaveFIFO to interface FPGA to FX3. If yes, please confirm if the GPIF threads are being driven properly by the FPGA. If FV, LV interface is being used the DMA buffers are used in ping pong manner as done in AN75779 default state machine

The image shared is not accessible to me. 

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