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Hi all,
In my design, I am sending continous data to FX3 without any clock. Whatever data comes to fx3, it will send to the PC. How should I configure the FX3 chip to read the data correctly?
I am generating 8 bit parallel data at 25Mhz externally and sending it through gpif. Is there any similar example design available? . Please note that I am not using any clock in the gpif design.
Thank you.
Solved! Go to Solution.
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Hello Dineesh,
You can configure the GPIF clock as internal in the GPIF II Designer tool
You can set the frequency of internal GPIF clock from the firmware by setting proper clock divider value (according to the rate at which data is sent. In your case 25 MHz)
/* Initialize the P-port. */
pibclock.clkDiv = 2; // This value should be >=4 when internal GPIF clock is used.
pibclock.clkSrc = CY_U3P_SYS_CLK;
pibclock.isDllEnable = CyFalse;
pibclock.isHalfDiv = CyFalse;
For 25 MHz Internal clock
If SYS_CLOCK is 384 MHz , pibclock.clkDiv value can be 15
if SYS_CLOCK is 403.2 MHz , pibclock.clkDiv value can be 16
Please let me know if any queries on this
Regrads,
Rashi
Rashi
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Hello Dineesh,
You can configure the GPIF clock as internal in the GPIF II Designer tool
You can set the frequency of internal GPIF clock from the firmware by setting proper clock divider value (according to the rate at which data is sent. In your case 25 MHz)
/* Initialize the P-port. */
pibclock.clkDiv = 2; // This value should be >=4 when internal GPIF clock is used.
pibclock.clkSrc = CY_U3P_SYS_CLK;
pibclock.isDllEnable = CyFalse;
pibclock.isHalfDiv = CyFalse;
For 25 MHz Internal clock
If SYS_CLOCK is 384 MHz , pibclock.clkDiv value can be 15
if SYS_CLOCK is 403.2 MHz , pibclock.clkDiv value can be 16
Please let me know if any queries on this
Regrads,
Rashi
Rashi
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Hi ,
Thank you for your valuable answer.
I have few doubts. If I do fx3 clock as internal, Do I need to connect this clock to the data source(extenal device) by wire?
I am not using any fpga.
External data generating system output is only 8 bit data. No io line for clock signal. This 8 lines are connecting to the 8 lines of gpif. Is this possible?
Thank You
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Hello Dineesh,
After configuring the GPIF clock as internal both in GPIF Designer tool and firmware, you don't have to connect PCLK pin.
Regards,
Rashi
Rashi
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Thanks a lot for this valuable information.
I will do the same. Then we use only 8 lines in the gpif(8 bit parallel data) for connecting external source through gpif. Correct?
Regards,
Dineesh.
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Hello Dineesh,
As you are using GPIF bus width of 8 bits, you should configure that in the GPIF Designer tool.
On configuring this you can connect GPIO 0- GPIO 7 to the external source and rest other GPIOs can be left unconnected.
You can refer to GpifToUsb example of the SDK which has a simple state machine with GPIF data bus width as 32 bits (you can change this to 8 bits) and clock as internal and pibclock.clkDiv = 4 ( you can set this value to get 25 MHz). The default state machine just samples the data on GPIF bus width and send it to USB block. You can modify the state machine and the firmware as per the requirements.
Regards,
Rashi
Rashi
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Thank You Rashi.
I will do the same. Have a nice day.
Regards,
Dineesh.
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Hi,
In the firmware,I didnot see pibclock.clkDiv variable. I have attached screenshot with this.
clockConfig.cpuClkDiv - This is the varible you mentioned for changing value for the required clock frequency. Right ?
Thank You
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Hello Dineesh,
I mentioned the changes to be done were for pib clock and not the cpu clock
The pib clock is set before initializing PIB block
In GpifToUSB example
void
CyFxApplnInit (void)
{
CyU3PReturnStatus_t apiRetStatus = CY_U3P_SUCCESS;
CyU3PPibClock_t pibClk = {4, CyFalse, CyFalse, CY_U3P_SYS_CLK}; // refer to the structure CyU3PPibClock_t for more details. Here 4 is the pib clock divider (pibclock.clkDiv)
/* Initialize the PIB block. */
apiRetStatus = CyU3PPibInit (CyTrue, &pibClk);
if (apiRetStatus != CY_U3P_SUCCESS)
{
CyU3PDebugPrint (4, "PIB Init failed, error code = %d\r\n", apiRetStatus);
CyFxAppErrorHandler (apiRetStatus);
}
Regards,
Rashi
Rashi
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Hi rashi ,
I tried with this modifications, Its working. But if I changed pib value (7 for sampling frequency of 50Mhz), few of the data is not correct.(In the attached figure, 85 is repeating 3 times. But it should repeat 2 times. Because data generating clock is 25 Mhz and firmware sampling rate is 50Mhz(384/7) ).
I tried with pib value of 15(25Mhz), Then also some data sampled is incorrect. What is the reason for this?
Do I change communication type from synchronous to asynchronous?
(test data is an 8 bit incrementing data)
Thanks
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Hello Dineesh,
You would need another control signal if you configure for asynchronous.
If the frequency at which data from the external source is coming is 25 MHz the pibclock.div should be 15. FX3 will sample the the data present o the GPIF bus at every clock edge.
- Please let me know the reason to configure it to 7 and not 15.
- How many times do you get errors like this
Regards,
Rashi
Rashi
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Thanks for the help.
How to make control signal in the design for getting zero error?
I am getting very little number of errors. But I want system without error. data is generating at 25Mhz. Same data is capturing the fx3 throgh gpif. Is the error because of the lack of flow control mechanism. Then can you explain how to make a flag for the error free data transfer?
I tried with pibclkdiv =7 for checking whether errors are coming or not.
Thank You
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Hello Dineesh,
To receive the data without error you should keep the frequency of the internal clock same as the rate at which data is output from external source.
You can refer to asynchronous slavefifo interface if you need some control signals / flow controls signals.
You can refer to the firmware in the SDK Path: ....\Cypress\EZ-USB FX3 SDK\1.3\firmware\slavefifo_examples\slfifoasync
But for this you need to control the signals from FPGA side. You can refer to the interfacing signals
Note: The bus width is configurable to 8 bits
For timing diagrams of these signals you can refer to application note AN65974
Regards,
Rashi
Rashi
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Thanks Rashi for your support.
I have one query about FX3S development kit. Can I test the same fx3 firmware (for eg: syncslavefifo firmware in application note AN65974) with Fx3s also?
I tested and showing streaming failed in streamer application. How to send data from Fpga to Fx3s?
Thank You