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USB superspeed peripherals Forum Discussions

Anonymous
Not applicable

I am developing project using CYUSB3KIT-003 and FMC interconnect board CYUSB3ACC-005.
EZ-USB FX3 can be used as slave FIFO connected to Xilinx FPGA, doc AN65974.
The interface between EZ-USB FX3 and FPGA:
flaga,
flagb,
flagc,
flagd,
SLCS#,
PKTEND#,
SLRD#,
SLWR#,
SLOE#,
A[1:0]

the USB FMC interconnect board(CYUSB3ACC-005) net name is CTL[12:0]
My question is: How to map  CTL[12:0] to the signals mentioned above

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1 Solution

Hi,

If you look into the "slaveFIFO2b_fpga_top.ucf" file in the AN65974 project you will find the mapping of each signal as follows:

"flaga" LOC = T7;

"flagb" LOC = M11;

"flagc" LOC = N11;

"flagd" LOC = N8;

"slcs" LOC = A7;

"pktend" LOC = M8

"sloe" LOC = P8;

"slrd" LOC = R7;

"slwr" LOC = N7;

"faddr[0]" LOC = N9;

"faddr[1]" LOC = M10;

Moreover I am attaching an image of interconnect board that will help you to map the signals.

Hope this will answer your question.

-Regards

Abhinav

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3 Replies
abhinavg_21
Moderator
Moderator
Moderator
50 likes received 25 likes received 10 likes received

Hi,

You have to map the desired signals in  "slaveFIFO2b_fpga_top.ucf" file. Please refer to the FPGA board Schematics and Interconnect Board Schematics to properly select the signals.

Thanks & Regards

Abhinav

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Anonymous
Not applicable

Thanks for your sincerely reply.

But I still do not get the desired answer.

I need the mapping relationship between ctl[12:0](in CYUSB3ACC-005) and below signals:

flaga,

flagb,

flagc,

flagd,

SLCS#,

PKTEND#,

SLRD#,

SLWR#,

SLOE#,

A[1:0], which are descripted in doc AN65974。

For example, in CYUSB3ACC-005, DQ0 pin is mapped with H4. In FPGA board Schematics, I can find the mapped signal of H4 in FMC JX is LA16_N. and then, LA16_N can be found mapped to AJ13 IN FPGA band10.

So I know DQ0 should be constrained to AJ13 in my .ucf file.

In doc EZ-USB FX3 Technical Reference Manual, spec No:001-76074 Rev. *E, about CTL[12:0] description is:

The GPIF II control signals (CTL[12:0]) can be configured as outputs to control the external peripheral device, or as inputs to read the status from an external peripheral device.

In doc AN 65974, EZ-USB FX3 used as slave FIFO connected to external FPGA. the interface between FX3 and FPGA is DQ[31:0], flaga, et al. I guess, there is a mapped relationship between and flaga and CTL[12:0].

But I didn't find the mapped relationship.

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Hi,

If you look into the "slaveFIFO2b_fpga_top.ucf" file in the AN65974 project you will find the mapping of each signal as follows:

"flaga" LOC = T7;

"flagb" LOC = M11;

"flagc" LOC = N11;

"flagd" LOC = N8;

"slcs" LOC = A7;

"pktend" LOC = M8

"sloe" LOC = P8;

"slrd" LOC = R7;

"slwr" LOC = N7;

"faddr[0]" LOC = N9;

"faddr[1]" LOC = M10;

Moreover I am attaching an image of interconnect board that will help you to map the signals.

Hope this will answer your question.

-Regards

Abhinav

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